Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 09 Oct, 2020 - Comments: 0

Security A new certification program for hardware verification engineers from Edaptive Computing Inc (ECI) and OneSpin Solutions promises to help companies meet IC integrity standards for SoC designs for 5G, IoT, AI, automotive, industrial, defense, and avionics. These designs are often complex, with a variety of elements, such as programmable logic and different cores. The OneSpin Formal Veri... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 28 Aug, 2020 - Comments: 0

Pervasive computing — data center, edge, IoT Marvell is working on silicon for the data infrastructure market using TSMC’s 5nm process node. Marvell says it has multiple designs already under contract for its 5nm portfolio across the carrier, enterprise, automotive, and data center markets. The first products are sampling by the end of next year. Ansys’ multiphysics signoff tools, R... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 12 Jun, 2020 - Comments: 0

Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: TSMC N5

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Auto, Security, Pervasive Computing

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Entities, people and technologies explored