tag: UVM

Beyond UVM Registers — Better, Faster, Smarter
By Mentor, a Siemens Business - 27 Jan, 2016 - Comments: 0

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex syst... » read more

Verification Grows Up
By Brian Bailey - 05 Jan, 2016 - Comments: 2

Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, President of Willamette HDL; Jin Zhang, VP marketing and customer relations for [getentity id="22147" comment="Oski Technology"] and Lauro Rizzatti, a marketing consultant and previously the general manage... » read more

A History of (Premature) Optimization
By Neil Johnson - 22 Dec, 2015 - Comments: 0

I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left writing and been advocating for agile development, this kind of comparison is more than a little odd to see. It’s a comparison between two as yet amorphous development strategies, neither of which i... » read more

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

HW Vs. SW: Who’s Leading Whom?
By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Appetite For Services Grows
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

Blog Review: Sept. 9
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

Making Hardware Design More Agile
By Ed Sperling - 31 Aug, 2015 - Comments: 1

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

From Simulation To Emulation
By Mentor, a Siemens Business - 12 Aug, 2015 - Comments: 0

This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain ... » read more

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