Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Valtrix Pushes For Horizontal Verification Reuse


Some of the most significant advances are not the result of a single person or a single idea. They often don’t happen overnight, and are suggested by a change that slowly becomes pervasive enough to become a generalized solution. That is exactly what is happening right now in the area of functional verification. The tools and methodologies in place at the moment assumed designs typical of the... » read more