New architectures, different markets and more variables make it increasingly difficult to design and verify low-power chips.
How good are standard FPGAs for AI purposes, and how different will dedicated FPGA-based devices be from them?
Seventeen startups took in mega-rounds of $100 million or more during October, with a cumulative total of just over $3.2 billion.
More nodes and alternative memories are in the works, but schedules remain murky.
Sixteen startups attracted funding rounds of nine figures in November.
New architectures, different markets and more variables make it increasingly difficult to design and verify low-power chips.
New materials, new architectures and higher density have limited what can be done with DRAM, but it’s still king (Experts At The Table Part 3)
Can the processor/memory bottleneck be closed, or do applications need to be re-architected to avoid it?
As chips grow in size, optimizing performance and power requires a bunch of new options and methodology changes.
The design of the power delivery network just got a lot more complicated, and designers can no longer rely on margining when things become vertical.
Through QED-C, the U.S. government helps build industry support behind quantum computing.
Arm’s CEO examines the impact of an explosion of data at the edge, 5G and heterogeneous architectures.
What are the worst-case conditions for a chip, and should you worry about them? Of course, it is a little more complicated than that.