Full-Chip Voltage Contrast Inference Using Deep Learning; You Only Look Once: Voltage Contrast (YOLO-VC)


Abstract: The electron beam inspection methodology for voltage contrast (VC) defects has been widely adopted in the early stages of sub-10nm logic and memory technology development, as well as in new product introductions. However, due to throughput limitations, full-chip inspection at the 300mm wafer scale remains impractical for yield ramp and production applications. To address this challeng... » read more

Modulated Electron Microscopy Applied In The Process Monitoring Of Memory Cell And The Defect Inspection Of Floating Circuits


A technical paper titled “In situ electrical property quantification of memory devices by modulated electron microscopy” was published by researchers at Hitachi High-Tech Corporation, KIOXIA Corporation, and Western Digital. Abstract: "E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam... » read more

New Method For BEOL Overlay And Process Margin Characterization


This paper presents a new method, design for inspection (DFI) to characterize overlay. Using design-assisted voltage contrast measurement, the method enables in-line test and monitoring of process induced OVL and CD variation of backend-of line (BEOL) features with litho-etch-lithoetch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned d... » read more

Advanced High Throughput e-Beam Inspection With DirectScan


Optical inspection cannot resolve critical defects at advanced nodes and cannot detect subsurface defects. Especially at 7nm and below, many yield and reliability killer defects are the result of interactions between lithography, etch, and fill. These defects often will have part per billion (PPB) level fail rates. Conventional eBeam tools lack the throughput to measure PPB level fail rates. A ... » read more