Raising IP Integration Up A Level

By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

A New Dawn For IP

By Brian Bailey - 12 Dec, 2019 - Comments: 0

The IP industry is changing again. The concept started as build once, use everywhere, but today it is more like architect once, customize everywhere. Few designs can afford sub-optimal IP for their application. The need for customized IP is driven by both leading-edge designs and the trailing markets, although for different reasons. While this customization is causing IP companies to transfo... » read more

Integration IP Helps IP Integration

By Brian Bailey - 08 Sep, 2016 - Comments: 0

You might not know much about the MIPI Alliance if you aren't designing mobile phones, but you will soon. Other application areas are taking interest in what this group has accomplished. The alliance was founded in 2003 to create standards for hardware and software interfaces in mobile devices. Successful examples include a camera serial interface (CSI) and a display serial interface (DSI), ... » read more

Can IP Integration Be Automated?

By Ann Mutschler - 24 Sep, 2015 - Comments: 1

What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

The Internet Of Cores

By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

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New techniques go beyond improved deposition and etching, but challenges stack up, too.

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Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

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Raising IP Integration Up A Level

A New Dawn For IP

Integration IP Helps IP Integration

Can IP Integration Be Automated?

The Internet Of Cores

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