Getting A Handle On RTL X-Verification Challenges

By Graham Bell - 27 Mar, 2014 - Comments: 1

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout. Some engineers point out that we have always had to deal with X’s and nothing has really changed. In fact, today’s SoC employ different power management schemes that wake-up or suspend IP. As any designer knows, when powering ... » read more

Are Designers’ X-Analysis Needs Different From Verification Engineers?

By Lisa Piper - 11 Nov, 2013 - Comments: 0

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. Besides the sheer complexity of these designs, the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip. This article describes a methodology that enables design an... » read more

Low Power Verification – “X” Marks the Spot

By David Hsu - 10 Oct, 2013 - Comments: 1

Welcome to a new discussion on a range of topics we think will be interesting to folks who design and verify SoCs. Though the name of this blog denotes two top attributes of SoCs—IP implementation and the pervasive need for low power (LP), we certainly may go far beyond the scope of these topics in upcoming posts. We’ll start with a topic on the LP side, and going forward we’ll alternate ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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tag: Xs

Getting A Handle On RTL X-Verification Challenges

Are Designers’ X-Analysis Needs Different From Verification Engineers?

Low Power Verification – “X” Marks the Spot