Tales From The Road

By Mike Gianfagna
We recently held a SpyGlass Power “boot camp” at Atrenta San Jose. We brought in 15 of our best and brightest field AEs from all over the world and discussed the very latest techniques for advanced power optimization.

When you get a group of folks like this together in one room, the learning typically goes both ways. The “students” (the FAEs) certainly learn a lot about new technology. But the “teachers” (the marketing and engineering folks) learn a lot, too. Field AEs are an articulate bunch. They are basically order-up experts on almost any topic and are essentially fearless. They say what’s on their mind, and the stories they bring back from their travels on the road can be incredibly valuable.

Such was the case during our SpyGlass Power boot camp. A lot of the conversation centered on RTL power estimation—why customers initially don’t trust the results, and how to overcome those concerns. We all learned a lot from these “tales from the road.” Here are some useful tidbits…

Generally speaking, total power from RTL power estimation has correlated well with gate-level numbers. At 28nm and below, designers are starting to look at the sub-components of power, such as combinatorial, sequential, memory, etc. This gives rise to the need for better correlation to make design changes and meet power budgets. A successful correlation strategy requires a good grasp of what is responsible for the differences between RTL power estimation and the corresponding netlist (post-synthesis) components.

There are a lot of sources for correlation mismatches. They include:

• Synthesis
• Simulation
• Annotation
• Capacitance
• Clocks
• Library cell usage
• Wire load models
• Slew/buffering

This is a daunting list. Is there a way to address these issues? It turns out there is a lot you can do if you know some tricks. Those tricks include the requirement that the synthesis that drives RTL power estimation needs to be fast and therefore should be area-based. Other tricks: Don’t use certain library cells and use particular drive strength cells only. (VT mix specifies the low/high threshold mix.) Use a custom wire load model generator for a particular technology node. Define clock tree characteristics at RTL and incorporate slew-based buffering to fix timing. Also, use power scaling of sub-components based on the technology node.

All this invariably leads to an RTL power estimation “bake-off,” where favorable correlation between RTL and gate-level numbers means everything. Schematically:

Is all this worth it? Our group of black-belt field AEs thought so. They have seen first-hand the benefits of optimizing power intent at the early stages of design, at a time when flexibility is greatest and options are most plentiful. It also appears that the folks designing mobile applications are ahead of the pack with this technology. Most have totally adopted RTL power estimation and run daily regressions for any functional changes and then recalibrate the gates from a gate level netlist on a monthly basis. The rest of the industry will soon go this route as well.

Deploying RTL power estimation is a winning strategy and thanks to our tales from the road, we know it works.