Tame IR Drop Like Google

In the relentless pursuit of semiconductor performance and efficiency, tech giants like Google are constantly pushing the boundaries of what’s possible. As they scale their designs to the cutting-edge 3nm node, power integrity has emerged as a critical challenge that must be overcome.

Enter Calibre DesignEnhancer (DE), Siemens’ analysis-based solution for enhancing design reliability and manufacturability. Google has turned to Calibre DE to tame the growing threat of IR drop, a pervasive issue that can undermine the performance and stability of advanced ICs, while maintaining design performance, power, and area (PPA) targets.

The need for a robust IR drop solution

The journey to 3nm designs has been driven by the promise of significant improvements in area, energy and performance. However, as transistor density skyrockets, power integrity has emerged as a key hurdle.

Designers faced two key problems:

• Dynamic voltage drop issues: Higher operating frequencies and increased current densities exacerbate dynamic voltage fluctuations, leading to potential performance degradation.
• Static IR drop challenges: Narrower and longer interconnects in 3nm designs result in more severe static IR drop, which can cause functional failures.

These effects can undermine the performance of critical circuit blocks and even compromise functional integrity. Addressing these issues through conventional P&R flows or manual layout tweaks often leads to additional design cycles, risking delays and increasing costs.

Designers found that the traditional approaches to addressing IR drop, such as design derating or power distribution network (PDN) redesign, proved to be ineffective and time-consuming. What is needed is a solution that could surgically target IR drop hotspots while maintaining design rule compliance and preserving their hard-earned power, performance, and area (PPA) targets.

Requirements of an effective EMIR solution

A robust electro-migration and IR (EMIR) solution must offer detailed insights into the layout for accurate electrical analysis and DRC-clean layout modifications. Among the key features of a solution are:

1. Layout-based accuracy: Accurate IR drop mitigation requires precise knowledge of the layout, which requires the tool to use detailed layout data, rather than estimates.
2. DRC-compliant modifications: Any layout changes must be DRC-clean to ensure smooth integration into downstream verification and sign-off flows.

Calibre DE uses both general and specialized Siemens’ SVRF commands to modify the layout and resolve EMIR issues in compliance with the latest DRC/LVS decks. This solution also leverages the foundry-specific DRC rules provided in the design kit, enhancing its reliability and usability for both CAD teams and designers.

Google’s methodology for IR drop mitigation

To meet their IR drop mitigation requirements, a structured methodology was developed. This approach focused on enhancing power grid robustness and maximizing via insertion across the layout. The methodology consisted of two primary steps:

1. Power grid enhancement with Calibre DE Pge: This tool adds and connects parallel metal stripes to the power grid to target specific IR drop hotspots identified in IR drop analysis windows. The tool avoided timing-critical nets, maintaining timing integrity while strengthening the power distribution network.
2. Via insertion with Calibre DE Via: To further reduce resistance, Calibre DE Via maximizes the insertion of vias across the layout. This automated via insertion was applied to all non-critical areas, ensuring robust connections without violating DRC rules. The integration of Calibre DE with industry standard P&R tools via DEF files streamlined this process, allowing layout modifications to be seamlessly backannotated for validation.

This two-step approach let designers focus their efforts on areas of the design where IR drop was most severe, reducing the need for over-design of the PDN.

Results: Significant IR drop reduction in a 3nm design

Google’s experiments on a complex 3nm design showed a remarkable 30% decrease in the number of instances with the highest IR drop levels. Crucially, the layout modifications were DRC-clean, ensuring seamless integration back into the design flow. The Google team shared results from two windows of a complex full-chip 3nm design that had IR drop hotspots.

These results highlight Calibre DE’s ability to address IR drop hotspots effectively while maintaining DRC compliance, allowing Google to finalize their design without costly manual rework.

Beyond the IR drop improvements, Google’s use of Calibre DE also delivered significant benefits to their overall design flow and time-to-market. The tool’s correct-by-construction approach eliminated the need for costly design iterations, reducing the overall development cycle. Additionally, Calibre DE’s seamless integration with multiple P&R environments gave Google the flexibility to leverage their preferred design tools without sacrificing quality.

This success with Calibre DesignEnhancer underscores the critical role that advanced EDA solutions play in enabling the next generation of high-performance, reliable semiconductor designs.

Addressing EMIR challenges across stakeholders

Calibre DE’s analysis-based layout modification capabilities cater to the needs of foundries, CAD teams, and designers:

• For foundries: Each new technology node introduces unique DRC/LVS deck requirements. Calibre DE incorporates these rules to ensure that layout modifications align with foundry standards, reducing support costs and enhancing manufacturability.
• For CAD teams: Calibre DE offers compatibility with various P&R tools, allowing CAD teams the flexibility to choose the best tools without compromising quality. The solution’s integration capabilities simplify workflows and increase usability.
• For designers: Designers benefit from the automated DRC-clean layout modifications provided by Calibre DE. The Calibre RealTime Digital GUI, which interfaces with leading P&R tools, enables designers to quickly implement layout changes, focusing on maximizing via insertion and power grid reinforcement without manual intervention.

Conclusion: A new approach to managing IR drop for reliable ICs

As IC design continues to scale to smaller nodes, managing IR drop efficiently becomes more challenging. Google’s recent work with Calibre DesignEnhancer illustrates a modern approach to chip finishing, focusing on IR drop hotspots to optimize power delivery without compromising PPA.

For design teams facing similar challenges, Calibre DE offers an automated, DRC-compliant solution that integrates seamlessly with existing workflows. Its analysis-based layout modifications provide significant IR drop mitigation while meeting stringent sign-off requirements.