The Brave New World Of Modeling TSVs

Through-silicon vias must be modeled in 3D ICs to fully understand their impact on the global design and the signal quality through this complex package structure.

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By Ann Steffora Mutschler
With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together.

As we start to stack chips they will interact from wire to wire on different chips, and the TSV is huge in comparison to the wires engineering teams are used to seeing. The TSV has significant resistance and capacitance effects, but it also has inductive effects that previously weren’t an issue other than with high frequencies. In 3D ICs the wires interact with each other and with the large vias—and it all has to be characterized.

To properly design the device, package and board, the TSVs must be modeled to fully understand their impact on the global design.

“Modeling TSVs is important for looking at the signal quality through this now pretty complex package structure,” explained John Park, methodology architect for IC packaging and pathfinding technologies, in the systems design division of Mentor Graphics “Where that complexity truly comes in, we’re talking about a cross-domain design tool. We’re talking about chip-level guys, package-level guys and board-level guys all trying to figure out how this off-chip interconnect network needs to be routed. And all of those guys have their own characterization tools or EM modeling tools or parasitic extraction tools.”

Antonio Ciccomancini Scogna, market development manager (global EDA) at CST of America, explained that the general idea to address the concerns related to 3D ICs and TSVs/silicon interposers is to use 3D electromagnetic (EM) simulation to electrically and thermally capture the physical behavior of such structures. “Electrical modeling of these interposers is not trivial especially for silicon substrates due to its lossy and semi-conducting behavior along with the multi scale dimensions involved.”

This is because the dimensions of TSV is in the order of few microns, the thickness of the oxide silicon surrounding them is a fraction, 0.2 microns or less. Large bandwidth of operation causes unexpected behavior from the materials involved in the 3D ICs.

Thermal effects also play a very important role in dictating both the IR drop and high frequency response of interposers, and this effect is exacerbated in 3D integration due to larger current densities that need to be supported. That results in hot spots in various parts of the system. In addition, Joule heating due to current flowing in interconnections can cause increased IR drop, he said.

Today’s EM tools are not adequate when it comes to TSVs because the small dimensions, high aspect ratio and complex physical phenomena involved with TSV makes EM simulation challenging. “Some of the complex physics to be modeled includes depletion area around TSV and skin mode to slow wave mode transition, as well as electrical and thermal performance,” Ciccomancini Scogna said. He added that 3D simulation is required because of the 3D nature of the ICs, interposers and system integration. Electrical outputs (current distribution and power flow) can be used to study and address thermal concerns.

CST (which partners with Cadence), Mentor, Ansys and others, has tools in this area that address some or all aspect of the electrical, thermal and multi-physics analysis.

Also to this end, Mentor Graphics has been working on modeling TSVs in a project with STMicroelectronics, with a beta release due out in Q3.

“When you actually start stacking logic on logic or using an interposer, we assume that TSV is single LVS, but that’s no longer true. It becomes a device that now has a different response based on its environment. It becomes contextual, and we want to know how it affects the electrical performance,” said Michael Buehler-Garcia, senior director of marketing for Calibre design solutions at Mentor Graphics.

Mismatched thermal coefficients
From the manufacturing equipment side of TSVs, Sesh Ramaswami, managing director of strategy for the silicon systems group at Applied Materials, explained that the company conducted joint research with Synopsys in 2009 and subsequently published a paper on their findings in 2010. “Essentially what we’re looking at is, because you have the copper in the material and then you have silicon outside, you have a natural coefficient of thermal expansion (CTE) mismatch. The copper expands more than the silicon, and you can’t change that. Given that, how do you minimize the mismatch on the device parametrics?”

“Based on what we learned from that modeling work,” he continued, “we did some development work on the fill process itself, which involves the plating chemistry and the plating process. So although there is mismatch between the coefficients of expansion, it still works from a device point of view. We also looked at stress levels. After you etch the hole, you have to put in an oxide liner and then you put in a barrier metal, and then a seed layer prior to plating. We looked at various methods of depositing the seed layer such that your assumed stress remains as neutral as possible. Of course things are never neutral but you try and mitigate the effects by using chemistry and process.”

To this end, Applied is currently qualifying the metals for this process.

Another issue with TSVs in the manufacturing process is the size of the TSV hole itself. “The bigger the hole, the bigger the impact on the transistor which is close to it. When I say close, there is a thing called keep out zone—how far the active device can be from the TSV,” Ramaswami noted.

To mitigate this problem, he pointed to research that Imec has done on the best way to organize the TSVs whereby the stresses can be canceled out by organizing the TSVs in a triangular, square or rhombus configuration.

Applied is also working to scale TSVs smaller to mitigate some issues with the keep out area.

At the end of the day, the industry is still very much is the R&D phases of TSV technology with new developments revealed frequently. What will be interesting to see is the use of TSVs in 3D ICs in mainstream design and manufacturing flows and how the challenges are addressed along the way.