The Future Of 3D Stacking

By Ed Sperling
Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed.

The first wave, which is expected to start showing up late next year, will likely come from a handful of top fabless companies that have been working seriously on this technology for the past half-dozen years. These are companies that typically generate enough volume to warrant the investment, primarily in the handheld consumer electronics market.

For them, the goal is to improve performance and lower power by shortening the wires between components. At 28nm and 20nm, cutting the distance a signal travels can provide a significant boost because once everything shrinks the distance between components can grow dramatically. By stacking one die on top of another, it takes less power to drive a signal because the signal has less distance to travel. And assuming the process is stable enough and the designs work, the first companies to market using this approach can greatly boost their profits over competing offerings using a standard single-plane approach.

“We’ve been finding people worried about the bend in a differential pair,” said Dave Kohlmeier, senior product line director for analysis products in Mentor Graphics’ Systems Design Division. “What they should be worried about is the length of the channel. “

He said the challenge of providing clean power to the IC is theoretically simpler in a stacked die, but there are still big problems to work out such as how the power will pass through the bonds, along with signal integrity issues of through-silicon vias located next to noisy components such as SerDes.

Start the revolution
Providing these issues can be solved—and most semiconductor companies believe they can—3D holds the promise of revolutionizing the chip industry. Rather than just re-using blocks of IP, entire chips can be re-used, either through stacking of older chips on top of others or by connecting them with an interposer inside a package.

This approach creates some very compelling economic benefits. First, it reduces the overall development cost of chips. Second, it allows companies to use older analog processes rather than struggling to redevelop analog blocks at the most advanced process nodes. And third, it allows them to mix the latest digital technology with anything they want, migrating from commercially available IP blocks to fully integrated, tested and verified platforms that can be attached to other chips.

For the semiconductor industry, which has stalled out over the rising cost, complexity and time it takes to design and verify chips at the most advanced nodes, this reduces risk and cost, and it allows individual companies to focus on their differentiating technology without worrying about developing an entire SoC from scratch.

Who’s on board?
Virtually all of the tools startups working around the edges of the big EDA vendors are investing heavily in 3D. The equipment makers such as Applied Materials have developed technology for manufacturing through-silicon vias. And companies such as Arteris have developed the interconnect fabric and interposer technology for connecting these chips together and linking together various busses such as ARM’s AMBA. The big bottleneck at the moment lies with the big foundries—GlobalFoundries and TSMC—which are quietly developing processes and experimenting with yield.

“The major foundries do not have standard rules at this point,” said Javier DeLaCruz, semiconductor packaging director at eSilicon. “We have a significant amount of R&D resources invested in this, but we haven’t started a design because without the design rules that can be tricky. The wafer foundries are now doing qualifying for their top five hitters. Once those guys are qualified and they iron out the wrinkles in the process then tier-two customers will get access. That’s when we’re going to see rapid growth.”

Most companies expect that transition in 2012. “The big trigger will be once the foundries release their TSV design rule sets,” DeLaCruz said. “After that the IP vendors will develop for 3D and you’ll start seeing ASICs and ASSPs rolling out.”

Business issues
Beyond the myriad technology problems, there are business issues to resolve, as well. The large EDA companies have been circumspect about their commitment to 3D. While most are convinced 3D stacking will happen, they need to understand what can be tweaked for 3D and what needs to be built from scratch. They also need to understand the economics of the tools they provide in a 3D world and whether there will be enough volume at a high enough price tag to warrant an investment.

Building a 3D stacked die with commercially available technology also raises questions about exactly who’s responsible if something goes wrong. “Who will the general contractor be,” asks Mike Gianfagna, vice president of marketing at Atrenta, which has just invested in a Grenoble design center for 3D technology. “Who takes the yield risk? And who takes the inventory risk?”

Those questions—and the answers—also may be different depending upon what exactly people mean by 3D stacking. Memory chips have been stacked for years. Using proven platforms is likely to be the next popular approach. But designing logic across multiple layers of die and optimizing signals and power across each layer so that multiple layers are part of a single holistic design will likely take far longer to materialize—if there is ever a business case that can warrant that kind of approach.

While companies are thinking several steps ahead, the real volume market is likely to lie somewhere between the “2.5D” interposer approach and the fully integrated multi-die approach. As with any cross-industry developments of this magnitude, there are no simple answers. But the good news is at least people are starting to ask the right questions.