Protecting data in memory even if isolation techniques are compromised.
Nowadays, as SoC (System-on-a-Chip) systems become more and more complex, security functions must grow accordingly to protect the semiconductor devices themselves and the sensitive information residing on or passing through them. While a Root of Trust security solution built into the SoCs can protect the chip and data resident therein (data at rest), many other threats exist which target interception, theft, or tampering with the valuable information in off-chip memory (data in use).
Many isolation technologies exist for memory protection such as UNIX kernel/user space partition and TEE memory protection. However, with the discovery of the Meltdown and Spectre vulnerabilities in 2018, and attacks like row hammer targeting DRAM, security architects realize there are practical threats that can bypass these isolation technologies.
One of the techniques to prevent the data accessed across different guests/domains/zones/realms is memory encryption. With memory encryption in place, even if any of the isolation techniques have been compromised, the data being accessed is still protected by cryptography. To ensure the confidentially of data, each user has their own protected key. Memory encryption can also prevent physical attacks like hardware bus probing on the DRAM bus interface. It can also prevent tampering with control plane information like the MPU/MMU control bits in DRAM and prevent the unauthorized movement of protected data within the DRAM.
Many of the major CPU and application processor makers are implementing memory encryption technologies in their latest microprocessor chips. For instance, x86 servers are now protected by using AMD SEV (Secure Encryption Virtualization) and Intel TME (Total Memory Encryption) based on an AES cipher. These are good examples of how memory encryption can be implemented.
New industry standards on SoCs are also making memory encryption part of their requirements. Examples are various DRM standards protecting 4K HDR content and new CPU architectures. For instance, in the latest Arm v9 architecture, the Arm CCA (Confidential Computing Architecture) employs memory encryption between realms.
As the leading provider of security IP, at Rambus we see the growing trend wherein SoC vendors want to employ memory encryption techniques in their ASIC or FPGA designs. In upcoming blogs, I’ll cover the major cipher algorithms used, as well as the design and implementation challenges for the instantiation of memory encryption in processor and accelerator chips.
Additional Resources:
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply