The Next SoCs

Industry leaders talk about the changes ahead and what’s causing the shift; emphasis shifts to software, platforms and stacked die.

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By Ed Sperling
The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips.

System-Level Design asked executives from across the SoC ecosystem what will change, what’s driving those changes and what the ideal SoC will look like in the next few years. Here are some projections, broken down by category:

EDA
Wally Rhines, chairman and CEO of Mentor Graphics—“The SoC at the leading edge will not be a standalone device. It will be adjacent or under other things, whether it’s a stack or an interposer, or whether it’s an SoC with memory attached. One big challenge we had was with the package verification tools for 3D. Rather than create one mega merge of GDSII we’ve had to do a careful partitioning of individual SoCs and interfaces. In our opinion 2.5D will overwhelm the other approaches for a while. Logic with memory and through silicon vias is in the early stages. An interposer with memory stacked on processors that are tightly integrated is much further along.”

Aart de Geus, chairman and CEO of Synopsys—“We’re looking at smart everything. There will be more and more cores with little IQs. There’s an Internet of people, but there’s also an Internet of things, which will be a combination of all capabilities and probably require a price decline. From a technological perspective this will be really hard, of course. But what’s new? The continuation of technology is still there and we still have all the same problems with test and verification. But we also have 25 years of backward compatibility.”

Lip-Bu Tan, president and CEO of Cadence—“Application-driven design will be the big shift. The software will drive the hardware and the hardware will drive the software. It will be both. At the foundatation will be complex digital blocks with analog blocks and key IP that has been optimized for the system. The reason is that the system guy now expects silicon and the entire hardware-software stack. Some of the apps and the IP will be able to be re-used, which will make the time to market shorter. Some will not. Right now the bottleneck is in the IP, software and total solution.”

Mike Gianfagna, vice president of marketing, Atrenta—“There are two threads to this. One is that the software guys will be driving the agenda. Software dictates the silicon and the battery life. You will have a rich library of building blocks put together against software requirements, and the hardware architecture will be abstracted so that software runs against that model. The second thread is that the tools will have to change. Early floor planning and physical analysis will be required with stacked die because there are multiple ways to put a stack together and you have to get it right the first time. A 3D stack will have to be planned and analyzed. There may be 20 possible ways to build it, but only one or two that make sense.”

IP
Simon Segars, executive vice president and general manager of ARM’s Physical IP Division—“The biggest change will be power management, which will require a collection of different processing elements. You won’t see a big, monster CPU in the future because that isn’t power efficient. The future will be distributed computing. It won’t be easy, of course. With software, physically building software that can deal with the whole system will be very difficult. There also is a big challenge in putting chips together in a cost-effective way.”

Simon Butler, CEO of Methodics—”The big challenge will be bringing business intelligence into SoC design. You need to know what EDA tools to use and what the quality is of the blocks that you are putting together. And you need to define the versions of all the IP blocks and where they’re being used around the company. The goal is to see a map of the IP fabric in a design. This isn’t being done today.”

Manufacturing/Assembly
Prasad Subramaniam, vice president of design technology at eSilicon—“SoCs will have to evolve into major platforms where 10% of the platform changes and there is commonality of 90%. Otherwise it will be completely unwieldy. That 10% will still be 20 million gates. That also includes the software infrastructure, which will allow you to do performance analysis at the system level and make tradeoffs at the architectural level.”

Tom Quan, director at TSMC—“At the advanced nodes we’re looking at baseband and digital for 28/20/14nm. We’ll need 2.5D and 3D to bring the rest of the system together. So we’re getting ‘More of Moore’ coupled with ‘More than Moore.’ There will be fewer design starts, but there will be more derivatives. The base platform will be programmable with a lot of diversity, so you may see a company sell a platform and build applications on that.”