The Week In Review: Design

Mergers & Acquisitions

Silvaco jumped into the IP market with its acquisition of commercialization and management company IPextreme. Founder and CEO Warren Savage will be staying on to head up the new division. Additionally, through wholly owned French subsidiary Infiniscale SA, Silvaco acquired a majority stake in edXact, which focused on parasitic reduction tools.

Rambus acquired the assets of Semtech’s Snowbush IP, adding high-speed serial interface IP to its portfolio for $32.5 million. The deal also includes payments based on specific new product sales through the end of 2022.

Tools

Mentor Graphics incorporated a version of the Calibre physical verification suite into the Tanner analog/mixed-signal physical design environment. Included tools are hierarchical design rule checking, layout versus schematic, and parasitic extraction.

ARM expanded its DesignStart initiative, which provides access to ARM Cortex-M0 processor IP with the ability to purchase a license later, to offer simplified and expedited access to EDA tooling and design environments from Cadence and Mentor Graphics.

Avery Design Systems uncorked the latest version of its tool for automation of analyzing X propagations in gate-level simulations using hybrid formal analysis. New additions include an improved setup process, database, and a built-in assertion to monitor DFFs.

EDA start-up Intento Design entered the market with a tool focused on automation of the sizing, biasing and migration of analog and mixed-signal IP across technology platforms.

IP

ARM released Artisan physical IP, including POP IP, for the new Cortex-A73 processor on the TSMC 16FFC (FinFET Compact) process. The first test chip incorporating the POP IP on the process taped out in early May.

Synopsys revealed a suite of new features for its 3200 Mbps DesignWare DDR4 IP, including expansion of memory capacity by up to 400% without degrading performance, reconstruction of all data in a failed DRAM with advanced error correcting code, and an embedded calibration processor to improve design margin and signal integrity.

Andes Technology revealed a quick start package focused on entry-level SoCs with a pre-integrated and pre-verified processor, fabric, and peripherals. The package includes the new N650 CPU IP, AE100 Platform IP, and AndeSight IDE.

Menta released a new generation of its embedded programmable logic IP cores for SoCs, which also added optimization for GlobalFoundries 14nm LPP process.

Arasan uncorked its MIPI DPHY IP Core Ver 1.2, supporting speeds of up to 2.5 Gbps per lane, on the TSMC 28nm HPC Process. The IP will soon be ported to TSMC’s latest HPC Plus Process.

Deals

Synopsys won a deal with NXP, which selected it as the primary provider of both emulation and SoC verification tools for automotive and secure connectivity applications.

Intel Custom Foundry certified Mentor Graphics’ physical verification and Analog FastSPICE circuit simulation platforms for Intel’s 10nm tri-gate process technology. Mentor and Intel Custom Foundry used a PowerVR GT7200 GPU design from Imagination Technologies for 10nm certification.

SMIC and Cadence teamed up to develop a 28nm low-power RTL to signoff design reference flow based on the IEEE 1801 low power design and verification standard.

SMIC and Synopsys also released a joint 28nm RTL-to-GDSII reference design flow.

Related Stories
Week in Review: IoT
Week In Review: Manufacturing