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The Week In Review: Design


Tools Synopsys updated its static timing analysis tool to use smart engineering change order (ECO) technology, which the company says reduces memory requirements by 5X and speeds runtime by 2X. The release also allows more scenarios on a single server, or flexible distribution to take advantage of customers' private compute clouds. IP Synopsys released MIPI display and camera interface... » read more

The Week In Review: Design


Tools Synopsys unveiled its next-generation ATPG and diagnostics solution, TetraMAX II. According to the company, the tool is an order of magnitude faster than the previous generation, reducing runtime from days to hours, as well as generating 25% fewer patterns. The new tool is also certified for the ISO 26262 automotive functional safety standard. It has been deployed by STMicroelectronics... » read more

The Week In Review: Design


Mergers & Acquisitions Silvaco jumped into the IP market with its acquisition of commercialization and management company IPextreme. Founder and CEO Warren Savage will be staying on to head up the new division. Additionally, through wholly owned French subsidiary Infiniscale SA, Silvaco acquired a majority stake in edXact, which focused on parasitic reduction tools. Rambus acquired th... » read more

The Week In Review: Design/IoT


Tools Synopsys unveiled a new custom design solution targeting FinFET layout, introducing visually-assisted routing automation, a built-in design rule checking engine, templates to apply previous layout decisions to new designs, and IC Compiler integration. TSMC certified the new tool for 10nm and 7nm FinFET process technologies. It has also been adopted by STMicroelectronics, GSI Technology... » read more

The Week In Review: Design/IoT


Tools Cadence unveiled Genus, their next-generation RTL synthesis and physical synthesis engine incorporating a multi-level massively parallel architecture and physically aware context-generation capability. Using it for their recent PowerVR GE7800 GPU, Imagination reported a 5X improvement in turnaround time versus the previous Cadence synthesis solution with no impact on power, performance... » read more

1-on-1 With Intel’s Foundry Chief


By Mark LaPedus & Ed Sperling Semiconductor Engineering sat down to discuss foundry trends, IC scaling, chip-packaging and other topics with Sunit Rikhi, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s Custom Foundry unit. SE: Where is Intel at in the foundry business today? Rikhi: We started with a very narrow set of customers. Now, we... » read more

Stacked Die Are Coming Soon. Really


Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more