The Week In Review: Design/IoT

Cadence unveils RTL synthesis tool; Atrenta extends Xilinx support; ARM’s IP tool suite; Mentor’s VIP productivity package; a wave of Intel 14nm certifications, plus UMC and SMIC updates.



Cadence unveiled Genus, their next-generation RTL synthesis and physical synthesis engine incorporating a multi-level massively parallel architecture and physically aware context-generation capability. Using it for their recent PowerVR GE7800 GPU, Imagination reported a 5X improvement in turnaround time versus the previous Cadence synthesis solution with no impact on power, performance or area.

Atrenta extended the SpyGlass platform for Xilinx Vivado Design Suite, providing support for CDC analysis on RTL designs with IEEE 1735 encrypted models and hard macros.


ARM announced a new suite of IP tools to address challenges associated with SoC configurability and assembly, including an IP design environment offering configuration, creation and assembly of ARM and third-party IP. They also unveiled a hardware subsystem for development of highly customized chips for smart connected devices. The ARM IoT subsystem for ARM Cortex-M processors is optimized for use with ARM’s processor and radio technologies, physical IP and ARM mbed OS, as well as TSMC’s 55nm ultra-low power process technology with embedded flash memory.

Mentor Graphics’ EZ-VIP productivity package for ASIC and FPGA verification teams using Questa Verification IP is now available. The package aims to increase productivity by reducing the time spent creating, instantiating, configuring and connecting up a QVIP testbench by 5X or more.

Foundries & Flows

A wave of tools were certified for Intel Custom Foundry customers on the 14nm platform: electromigration and dynamic voltage drop from Ansys; implementation and signoff from Cadence; digital and custom implementation from Synopsys; and reliability verification checking from Mentor Graphics.

UMC is developing an IC reliability reference flow for its customers based on Mentor’s Calibre PERC reliability verification tool, which will also be incorporated in SMIC’s third party IP certification process.

eSilicon added SMIC as a new foundry choice for its GDSII Explorer online quoting tool. The SMIC option will be available commercially in July 2015.

As part of TSMC’s soft IP QA program, Atrenta released a new IP Kit. Based on the SpyGlass 5.4.1 release, it aims to improve usability with native Tcl support for an interactive use-model, and is aligned with GuideWare 3.0 checks and best practices for IP design. It won Atrenta a deal with Sibridge, which adopted the kit as part of their IP Signoff flow.


Synopsys inked two deals for its rail signoff solution for static analysis: Toshiba says it will be used for all product lines, including mixed signal, ASIC and memories; and was adopted by Chinese company Nationz. Plus, STMicroelectronics taped out their latest 28-nm-FD-SOI SoC using Synopsys’ place and route solution.

The Hamburg Port Authority and NXP jointly unveiled the first intelligent traffic light for the port of Hamburg. To optimize the flow of truck traffic through the increasingly heavily used port, a Vehicle-to-X (V2X) system allows vehicles to communicate securely and wirelessly with traffic lights, road signs, and roadworks. An approaching line of vehicles can communicate with the light to turn it green or keep it green, allowing the vehicles to pass the light without stopping. In addition, RFID allows the traffic light to identify vulnerable road users in the vicinity and send automatic hazard warnings to approaching trucks.

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