Stacked Die Are Coming Soon. Really

After years of imminent predictions, economics finally are pointing toward vertical packaging.


Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner.

But something very fundamental will change after 14nm, namely the cost equation that has driven Moore’s Law since 1965. After that, it becomes significantly more expensive to proceed with fully integrated ASICs by simply shrinking features. It’s not just the design and integration side, either. Yield plunges as chip sizes increase, making it far more expensive to manufacture fully functional chips, while the number of patterning steps per layer rises at each new process node.

“Double patterning will need two passes per layer. At 7nm you will need four passes per layer,” said Samuel Wang, vice president of research at Gartner. “And with bigger die, the yield drops fast.”

Wang said that for a 100mm² die, yield drops from 500 good chips per wafer at 28nm to 419 at 7nm. For a large, complex 400mm² die, the yield drops from 63 to 31. In contrast, yields are significantly higher using smaller die packaged together compared with one highly integrated large die.

This is very good news from a power and performance standpoint. Fatter pipes with Wide I/O (versions 1 and 2), less distance that signals have to travel, and simpler layouts in terms of connection between logic and memory, make the power/performance characteristics of 2.5D and 3D architectures extremely attractive. As a result, the first adopters are likely to be network infrastructure providers and high-performance computing centers, but the technology becomes much more attractive to many more segments as the cost and complexity of scaling increases, particularly after 14nm.

This equation hasn’t been lost on manufacturers, though. They’re racing to prepare for this architectural shift. All major foundries, EDA vendors and OSATs (outsourced semiconductor assembly and test providers) are readying flows, tools and integrated processes that are expected to be utilized for production chips late next year and into 2016.

Even Intel has begun separating embedded DRAM out from the processor in a package, and expects to pursue 3D stacking for foundry customers. The company also has been quietly experimenting with die stacking for about the past four years. “Development is happening on all fronts all the way up to full 3D,” said Sunit Rikhi, general manager of Intel Custom Foundry. “And system in package offers performance, bandwidth and lower power.”

Rikhi noted that Intel continues to drive toward advanced nodes, as well. But he added that customers are asking for multiple packaging alternatives, which will begin showing up on the market next year.

Economic shifts
The recognition that significant change is occurring was a dominant theme at both Semicon West this week and the Design Automation Conference last month. Moore’s Law will continue, but not for everyone, and possibly not for economic reasons for anyone. Even more important, it will not continue for all components even for companies that will continue to push to the next process node.

“The greatest challenges below 14nm are device scaling due to pattern complexity and lack of EUV readiness,” said An Steegen, senior vice president of process technology at Imec, the Belgian research house. “3D stacking has seen slower adoption because of cost, but we see great incentives for saving in other ways (using this approach).”

Cutting through the confusion
Equipment makers view 3D in two ways, which tends to be confusing outside of sometimes narrow segments. For example, metrology on 3D may include finFETs, 3D NAND and TSVs, while from a packaging standpoint they are completely different. Terminology can mean different things to different people, depending on where they are in the supply chain.

Also adding to the confusion is 2.5D, which initially was suggested as a half-step toward 3D, using interposers instead of TSVs. Consensus among analysts, chipmakers and foundries is that both will co-exist for many years to come, depending upon thermal considerations, flexibility in packaging, ease of test and time-to-market considerations.

The reality is that all approaches will be pursued aggressively, and if extreme ultraviolet lithography becomes commercially viable, it will be used in addition to 193nm immersion. But even EUV requires double patterning at 7nm, so while it will help reduce the steps, it won’t solve everything. And with interconnect technology running into problems at 10nm, along with eDRAM, all signs point to stacking of die, either in a package connected with an interposer or silicon photonics, or with die on top of die connected with interposers.

“SiP is an important trend,” said William Chen, an ASE Group fellow. “When you look at the Internet of things, there are three things that will drive this—intelligent sensing devices, connected applications and a backbone network with bandwidth and storage. SiP technologies will be used for all three.”

He’s not alone in seeing that shift, either. In his annual presentation to analysts this week, Martin Anstice, president and CEO of Lam Research, cited what is widely perceived to be an inflection point in the semiconductor industry as it shifts gears to multi-patterning, finFETs and new packaging approaches. He said there is still a healthy appetite for finFETs, but there is also a huge opportunity for advanced packaging with TSVs in 2015 and 2016—to the tune of 70% to 120% growth for the company’s served available market.

And that’s just one piece. “From 2014 to 2017, inflection spending will essentially double,” Anstice added.

Heavy investment
Lam, Applied Materials and KLA-Tencor all have been working on making this packaging approach possible for years.

Rob Cappel, senior director of marketing at KLA-Tencor, said 3D metrology involves not just the critical dimension, but also the shape and the profile. “This is not just about litho etch,” he said. “It’s about the number of curves, the bowing of the wafer, the film deposition, CMP and the backside particles.”

And on the EDA side, all of the major vendors have been working to automate everything from layout to identifying what will cause thermal runaway, ESD and electromigration. But getting a handle on this, particularly from the tools side, is still fuzzy.

“3D design is more modular,” said Geir Eide, product marketing manager for diagnosis/yield products at Mentor Graphics. “But what happens if you stack them a different way? The test access might be similar, but the results might be very different.”

He noted that in recent months, there has been a significant shift from gate-level testing to transistor-level testing. “This is not just about ensuring coverage. It’s also about doing experiments to determine if you have a problem, and there isn’t just one answer.”

The tools and the processes will improve, as will the knowledge of what to do and what not to do. But until there is a body of knowledge from real-world production, getting a firm handle on how to optimize tools and what’s missing is hard to determine.

The upside
Still, the upside promise is huge. Gartner’s Wang said the advantages of full 3D stacking are a smaller footprint, improved integration density, decreased back end of line RC delay, improved transmission speed, a 30% power decrease, and faster time to market.

“The market drives the technology, and the market has not been ready,” he said. “3D-IC was ahead of its time, and there has not been a significant competitive advantage over 2D-ICs.”

But he said that after 14nm, the equation will change. And at that point, so likely will every part of the semiconductor supply chain and the industry as a whole. And even though Moore’s Law will continue to shape technology at the leading edge, there will be an increasing number of elements alongside the most advanced technologies that don’t fit under that umbrella anymore.



Dev Gupta says:

there is not bit of convincing data here that 3-d die stacking is imminent, the technical issues had not been disclosed by various Govt. funded labs overseas and as a result the Blogger community fell for it. Not even the current Intel announcement about using Micron’s HMC sometime in the future entirely convincing about imminent use of 3-D Memory / Processor stacks in the Consumer Electronics area ( GPU, SoC and all the rest ). The advantages of short interconnect possible with TSVs have to balanced against process complexity ( where are the yield figures 6 to 7 years after development ? ). It is only now that bond / debond as well as thinned wafer handling issues after via reveal are being addressed. Effects of stress / CPI as well as heat accumulation in the interior of the stack in device performance ( refresh rate ) is a huge non – linearity. TSVs look good in Power Point engineering but without the mature resources of IDMs its development by various small players and newbies like even large Foundries have been incompetent.

Bruce Burnworth says:

stacked die . . . how about one chip that has memory and processing? . . . one chip that is an entire computer . . . the IoT needs it . . . it will be produced . . .

Bruce Burnworth says:

Necessity is still the mother of invention . . . .

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