Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

HBM4 Sticks With Microbumps, Postponing Hybrid Bonding

By Bryon Moyer - 13 Jan, 2026 - Comments: 0

The next generation of high-bandwidth memory, HBM4, was widely expected to require hybrid bonding to unlock a 16-high memory stack. A JEDEC move made that unnecessary with this generation, but it’s merely a postponement, not a cancellation. HBM has been in high demand for AI in data centers — especially for training. Data movement dominates energy consumption, and high-bandwidth memories... » read more

Voltage Regulation Moves Into The Package

By Bryon Moyer - 29 Sep, 2025 - Comments: 0

Integrated circuits require a variety of voltages and a wide range of currents, typically supplied by voltage regulators. But increasing power density is resulting in higher power delivery losses. Moving those regulators closer to the chips they power can reduce those losses. Co-packaging them holds the most promise, but it comes with challenges. “What people have been talking about, ev... » read more

Critical Challenges and Opportunities Related to Polymer-Based Materials in Semiconductor Packaging (NIST, NC State, NREL et al)

By Technical Paper Link - 11 Sep, 2025 - Comments: 0

A new technical paper titled "Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science" was published by researchers at the National Institute of Standards and Technology, North Carolina State University, National Renewable Energy Laboratory, ASE, Intel, Innocentrix, and Binghamton University. Abstract "This Perspective builds up... » read more

Assembly Design Rules Slowly Emerge

By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Integrated Design Ecosystem For Chiplets And Heterogeneous Integration In Advanced Packaging Technology

By Lihong Cao - 23 Jan, 2025 - Comments: 0

As the demand for high-performance computing (HPC) continues to grow, chiplets and heterogeneous integration have emerged as key solutions due to their significant advantages in improving yield, reusing IP, enhancing performance, and optimizing costs. The integration of chiplets, particularly for AI applications, necessitates a greater number of connections than traditional monolithic system-on... » read more

Electrifying Everything: Power Moves Toward ICs

By Gregory Haley - 23 Jan, 2025 - Comments: 1

As electronic systems grow increasingly complex and energy-intensive, traditional power management methods — centered on centralized systems and external components — are proving inadequate. The next wave of innovation is to bring power control closer to the action — directly on the chip or into a heterogeneous package. This change is driven by a relentless pursuit of efficiency, scala... » read more

Accelerating The AI Economy Through Heterogeneous Integration

By Yin Chang - 17 Dec, 2024 - Comments: 0

The world is rapidly transitioning from an internet economy to an AI economy. In the internet economy, we stayed constantly connected to the internet 24/7 through our smartphones, PCs, and IoT devices. However, in the AI economy, every aspect of our lives is interwoven with artificial intelligence. You may already be familiar with AI tools such as ChatGPT or Google Gemini, which answer question... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging

By Gregory Haley - 21 Nov, 2024 - Comments: 1

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

ECTC 2024 Session Readout: Advancement of Metrology

By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A Electronic Components and Technology Conference (ECTC) session report titled "2024 ECTC Special Session Report: Advancing Metrology for Next-Generation Microelectronics" was published by NIST, Binghamton University, and TechSearch International. Abstract: "Metrology plays a pivotal role in semiconductor research, manufacturing, packaging and assembly. It is critical to the success of this... » read more

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