The Week In Review: Design

Bluetooth 5; hierarchical STA; DisplayPort 1.4 VIP; multicore software company gets funding.



The latest version of the Bluetooth standard was ratified by the Bluetooth Special Interest Group. Key updates in Bluetooth 5 include four times range, two times speed, and eight times broadcast message capacity, as well as updates that help reduce potential interference with other wireless technologies.


Synopsys updated its hierarchical static timing analysis tool for timing closure and signoff across all design sizes and levels of complexity. New capabilities automate partitioning and distribution of full-chip analysis across a company’s private compute cloud and allow block-level model analysis to be re-used throughout the flow.

Synopsys also released the latest version of its tool for the design of optical communication systems and photonic integrated circuits at the signal propagation level, adding Gaussian noise model for faster long-haul optical fiber simulation and support for the AIM Photonics PDK.


CEVA debuted IP for the new Bluetooth 5 standard consisting of a hardware baseband controller, a digital modem, and a software protocol stack.

Synopsys launched VIP and a source code test suite for DisplayPort 1.4 with DSC 1.2 and for eDP 1.4a/b. DisplayPort 1.4 features display stream compression (DSC) for visually lossless low-latency algorithms, increased resolution and color depths, and reduced power consumption.

Smartlogic released PCI Express DMA IP for Intel FPGAs. The IP was already available for Xilinx.


Silexica completed an $8 million Series A round of financing led by Merus Capital. Founded two years ago, the company’s focus is tools for complex multicore architectures.

Related Stories
Silexica: Multicore Software Automation
German startup analyzes numbers and types of cores, compiles software.
System Research Bits: Dec. 6
Computers that read (UCLA); Custom drones (MIT); 3-atom-thick chip prototype (Stanford)
Timing Closure Issues Resurface
Adding more features and more power states is making it harder to design chips at 10nm and 7nm.

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