The Week In Review: Design/IoT

Rambus developing chips; Accellera releases SCE-MI 2.3; Raul Camposano new Sage-DA CEO; Ansys and Imperas university programs; eSilicon adds specialty analog foundry CSMC while Real Time Logic joins Andes’ IoT hub; Synopsys’ Coverity adopted by Vietnam’s largest IT company; Mentor and Synopsys post financial results.



Rambus moved into the fabless market with the announcement that it is developing memory controller chips, expanding the company’s business beyond just creating IP for the memory and security markets. Read Ed Sperling’s full analysis.


Accellera updated the Standard Co-Emulation Modeling Interface (SCE-MI). The newest version of the standard, SCE-MI 2.3, expands the set of SCE-MI compliant DPI function argument data types, giving users less restrictions and more opportunity for design portability; extends the debug interface to provide C-side access to HDL-side registers, making the design on the emulator more accessible and debug easier; and adds a new mechanism that enables a SystemVerilog HVL-side testbench to call DPI functions to HDL-side SystemVerilog and vice versa, removing limitations in emulation usage.


Dr. Raul Camposano joined Sage-DA as its CEO. Formerly, Camposano was CTO, senior vice president and general manager at Synopsys for over 10 years. He also served as CEO of startups Xoomsys and Nimbic (acquired by Mentor Graphics). “The physical verification demands created by the escalating complexity of advanced process technologies cannot be efficiently met by today’s outdated methodologies and tools,” said Camposano. “Sage’s design rule compiler is a game changing technology.”


Ansys released a free, introductory academic software package for students interested in learning the fundamentals of simulation while gaining exposure to Ansys simulation workflows, pre-processing, post-processing and solver solutions. Students can tackle a broad scope of mechanics and fluids simulations, from fundamental tutorial level models to complex real-world scale models.

Imperas’ University Program is also on a roll. The program, which provides free access to open virtual platforms models and Imperas software development, debug and test tools, highlighted five recent projects and presentations.

CSMC Technologies, a pure-play specialty analog foundry, was added to eSilicon’s automated online quote system for multi-project wafer (MPW) shuttles. CSMC’s analog process platform includes mixed signal, HV-CMOS, BCD, RF-CMOS, e-NVM, DMOS, Logic, BiCMOS, IGBT/FRD and MEMS.

Real Time Logic joined Andes’ IoT platform, adding its secure connectivity portfolio for embedded devices to deliver dynamic control, fast enterprise-level security, and web functionality for industrial control, building automation, military, medical, and consumer markets.

Synopsys’ Coverity static code analysis solution has been adopted by FPT Software, part of the largest IT company in Vietnam. The company provides full lifecycle services including software design, development, migration and modernization. FPT cited an evaluation which identified “relevant problems with fewer than 10% in both false positives and false negatives.”


Mentor Graphics posted financial results for its second quarter with revenues of $281.1 million, up 8% from the same period last year. For the full year fiscal 2016, the company is raising revenue guidance to about $1.285 billion.

Synopsys also reported results for its third quarter of 2015. Revenue was $555.8 million, an increase of 6.5% over Q3 2014. The company “expects to exit the year with approximately 10% non-GAAP earnings per share growth,” said Aart de Geus, chairman and co-CEO of Synopsys.

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