Soitec COO Paul Boudre discusses what will be the best solution for 20nm – fully depleted silicon on insulator or bulk 3D transistors? The answer will likely include both.
Paul Boudre, COO of Soitec, talks with Semiconductor Manufacturing & Design about why SOI has suddenly become so interesting in semiconductor manufacturing and how it will affect the move to FinFETs.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
Pitches continue to decrease, but new tooling and technologies are required.
Buried features and re-entrant geometries drive application-specific metrology solutions.
Issues involving design, manufacturing, packaging, and observability all need to be solved before this approach goes mainstream for many applications.
Etching tools are becoming more application-specific, with each new node requiring higher selectivity.
While terms often are used interchangeably, they are very different technologies with different challenges.
Technology and business issues mean it won’t replace EUV, but photonics, biotech and other markets provide plenty of room for growth.
Commercial chiplet marketplaces are still on the distant horizon, but companies are getting an early start with more limited partnerships.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
How customization, complexity, and geopolitical tensions are upending the global status quo.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Key pivot and innovation points in semiconductor manufacturing.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
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