To Shrink Or Not To Shrink…And How Much?

By Ann Steffora Mutschler
The 28nm semiconductor manufacturing node is in full swing with 20nm process development ramping quickly. As such, the industry has been looking ahead to the next node shrink to achieve the power, performance and cost advantages that a node shrink promises. However, as we are well aware by now, traditional CMOS planar technology is not scaling as it did in previous generations, leaving many to scratch their heads about whether to move to 20nm or skip it altogether and embrace a new sub-20nm transistor type.

“We’ve done quite a bit of work on 20nm and now customers are asking whether they should start implementing their SOCs on 20nm or wait,” said Navraj Nandra, senior director of marketing for DesignWare Analog and MSIP at Synopsys. “There’s a big investment to go from 28 to 20 and if you’re going to make that investment why don’t they just go to the new FinFET. Those are some of the conversations I’m having at the moment. That impacts IP companies and it impacts fabs. It impacts everybody.”

Node skipping is happening across the semiconductor industry. “We do see a lot of customers looking at the risk versus the reward of going to 20 first, then 14, or skipping 20 and going to 14,” observed Jean-Marie Brunet, product marketing director at Mentor Graphics. “In terms of back-end layers, which are the metal interconnect layers, they are very, very similar between 20 and 14. The difference is only within the gate—the gate is basically finFET. All the advanced customers are looking at the raw performance of the transistor at 14nm being finFET and comparing that in terms of cost and risk. Is it better to go directly to a 14nm implementation or going to a 20nm, where the transistor is traditional bulk CMOS and it is not finFET yet? There’s no one-size fits all here. Not everybody is going to skip 20nm, but we do see a lot of customers considering actually going right away to finFET because the performance of the transistor is much better, so there is a considerable return here which, I think, is worth the risk.”

20nm is a different animal than traditional CMOS because it requires the insertion of double patterning throughout the design flow, which is a big challenge for custom designers. Back-end designers have to consider floorplanning, placement and routing. They have to consider the impact of overlay between the two masks on the extraction. There are a lot of different things throughout the design flow that double patterning is actually impacting, he noted.

Weighing all of the options and making the tradeoffs as to the possibility of skipping a node is no small task. “At 20nm there is a unique type of value proposition: ‘Which layer do I decide to do double patterning with? If I do double patterning then obviously the pitch is divided because I’m going to have two masks, so I’m going to have some tradeoff area.’ We see customers at 20nm taking a different approach. Certain customers consider double patterning only on the really low, front-end metallization layers, and others go all the way to what they can in terms of a metal stack. And they have different results,” Brunet explained.

EDA vendors aren’t saying which one is a better choice, but there is a cost element to consider. “We see some trends in terms of maximum area and die size that they can achieve if they take one approach versus the other one,” he added. “The one that goes double patterning all the way takes a little bit more time to put the design flow in place because it’s obviously more challenging, so they take a risk there. Others are a little bit more conservative—the area is not that good. So it’s a tradeoff of cost and time. And I think that’s why a lot of them are considering skipping a node and going to 14nm right away. They’re going to have a high risk, but the return might be much, much greater.”

EDA investment
From an investment point of view, EDA vendors invest in multiple emerging nodes simultaneously. Synopsys claims to have invested in several, according to Swami Venkat, senior director of marketing for the Galaxy Implementation Platform at Synopsys. “A while back we had to start with 20nm investment at the same time we had customers working at 14 or 16, and there are discussions at 10, so clearly from an R&D point of view we have to invest in multiple different nodes simultaneously.”

Before the foundry starts working on a process there is a significant collaboration that involves TCAD: 3-D modeling of devices must be done, the process geometry needs to be described, studied and analyzed. “Very early on, even before the foundries have announced a 0.1 version, we are working with them on the TCAD side,” he noted.

The transistor musketeers
Currently, there are three main options being debated as the transistor of the future: finFET, fully-depleted SOI, and a third created by SuVolta, according to the company’s senior vice president of marketing and business development, Jeff Lewis.

The DDC transistor a planar CMOS-based transistor, but it is structured differently to achieve some significant benefits. An undoped channel lessens the variability of the transistor, improves drive current and drive strength, and is still compatible with CMOS flows, he said. “If you look at a finFET or fully depleted SOI, all three share the same characteristic of an undoped channel and therefore the benefits of tighter variation, the ability to run at lower voltages with higher performance. That’s really where the industry is going. Everybody wants to transition to undoped channels because that gets you the power and performance advantages that are really starting to peter out in conventional CMOS. If you really think about it, there are these three types of transistors that are emerging to go to the next generation.”

How many will skip?
As for how many semiconductor companies will actually skip the 20nm node, that isn’t clear just yet.

“What’s going to happen is that for a while 28nm is going to be a popular node—probably a lot longer than previous nodes. There will be a lot of interest in the new finFET technology, and then the question is will the IP companies and the fabs be able to produce IP and the technology, respectively, for finFETs? If that’s the case then people may skip 20. If that’s not the case, and there are a lot of work and challenges along the way, we may see a reversal of that decision and people going back to evaluating 20nm,” Synopsys’ Nandra pointed out.

The real challenge is for the foundries, he said. “EDA companies will build what’s needed. As long as the design rule manuals are predictable and stable we’ll be fine. The question is really for the foundries.” Recently TSMC discussed a modular finFET approach with a16nm front end, but the back end is still 20nm.

TSMC told System-Level Design it currently is accepting customer test chips for 20nm. A comprehensive design ecosystem with Reference Flows and design kits, EDA and IP readiness, is complete. Volume production for 20nm will commence in late 2013, early 2014. In late 2013, TSMC will begin risk production of 16nm FinFET. An EDA and IP enablement program is underway. This includes collaboration with ARM to optimize their 64-bit A57 core for 16nm FinFET process.

GlobalFoundries is taking an even more aggressive approach with a 14nm finFET front end, and a 20nm foundation, explained Subi Kengeri, vice president of advanced technology architecture in the office of the CTO at GlobalFoundries. “The node skipping is something that’s inevitable at this point. 20nm was the first time double patterning was introduced and the manufacturing cost was definitely a big challenge. And if you look at the history of node adoption over the last few nodes, typically customers are used to expecting roughly around 30% die cost improvement going from node to node. That’s one of the motivations to move from node to node. But if you don’t get that directly in terms of die cost, then there has to be something to offset and compensate for that. We look at PPC (power, performance and cost) in an aggregated fashion. Somewhere, somehow, there needs to be a product-level value for customers to move to the next node. If they don’t see that, they will stay on that current node. Today that node is 28nm. Moving from 28nm to the next node, whether it’s 20 or 14, will be the main consideration for most of the customers, ecosystem, EDA, IP and everybody,” he said.

Going from 28 to 20, which are both planar technologies, the die shrink is achieved but not necessarily the full cost advantage.

“From a technology point of view, there’s no voltage scaling and so we had to find a different way to move to the next node to regain all the PPC value in some way,” Kengeri said. “That’s where finFET comes into play. FinFET gives you all of the technology advantage to operate at a lower voltage, and now suddenly you have an option to continue your technology scaling. But the finFET can be on a more advanced node, which means since we already have a 20nm planar, the whole industry could have considered putting finFET on the next node, which would have been 14nm. That’s where all the real discussion comes in and there are a number of angles to this: designability, technology, business.”

Because the industry has already made enormous investments at 20nm on the order of $50 million to $80 million for a design infrastructure, semiconductor companies have to leverage and extend that investment and the value to the product, he noted. That also will serve to extend Moore’s Law scaling, which hasn’t run out of steam yet.

To learn more about this from the manufacturing side, please see: “Node Skipping Reaches New Heights.”