Top-Down SoC Verification

Why UML-based scenarios are so important for SoC-level verification.


In the world of system-on-chip (SoC) verification, 2014 was an interesting year of transition. After much discussion throughout the year about graph-based techniques and the role of software for verification, we at Cadence ended the year with a bang – last week we announced Perspec System Verifier. The customers with whom we’ve been working on this product for years tell us that this is a big thing. It enables verification tasks they were not able to do before. What constrained random was for block-level verification, UML-based scenarios in Perspec System Verifier are for SoC-level verification!

But let’s roll back almost a year. At DVCon 2014, I was on a panel in which we had a somewhat heated debate about graph-based verification. Semiconductor Engineering wrote about this panel in the three-part series, “Big Shift in Verification.” Later that month, I was on a panel at DATE called “Future SoC verification methodology: UVM evolution or revolution?” At DAC I had organized a roundtable with Brian Bailey on the same topic – how will software change verification, and is UVM able to scale to the SoC level?

We all agreed – UVM does not scale to the SoC level. The software in modern SoCs breaks it. In addition, requirements of vertical and horizontal re-use, combined with the need to execute on all available validation engines – as described in “The Next Big Shift In Verification” – have become so critical that the next big step in verification has become necessary. Traditional bottom-up dynamic verification for IP and sub-systems needs to be augmented with top-down SoC verification based on use cases that translate into C-based tests executed as software-driven verification.

What does this all mean?
Consider a use case that is articulated top-down by an architect as, “View a video while uploading it.” This six-word statement translates into bare-metal actions at the SoC level that need to be executed in a form like “Take a video buffer and convert it to MPEG4 format with medium resolution using any available graphics processor.” Then transmit the result through the modem via any available communications processor and, in parallel, decode it using any available graphics processor and display the video stream on any of the SoC displays supporting the resulting resolution.”


Think about the state space that this use case creates! Various resolutions, different video algorithms, different resources, different types of memory buffers, and so on. Writing such a test manually, if even feasible, is hard to do and requires valuable system knowledge. And then the resolution, memory, or resources change – which makes it harder. This is where UML-like use-case definitions and constrained-random solving techniques to instantiate data and control flow with valid combinations of parameters come in as shown in the figure associated with this post.

The abstract use case reads from a memory buffer, converts data into a second memory buffer, and then in parallel transmits and decodes for display. The UML-based description is intuitive and can be understood by the various stakeholders. The automation involved transforms this description into an actual UML activity diagram with randomized video buffers, specific choices of video conversion formats like MPEG4 to save into specific buffers, randomized video stream attributes, random selection of a display for the stream playback, and distribution across available compute resources.

Wouldn’t it be nice to combine this capability with automatic generation of the associated tests that execute on the processors in the design, and run them on the various validation engines of the System Development Suite – from virtual platforms through RTL simulation, emulation, FPGA-based prototyping, and the actual silicon? Well – that is exactly what our most recent announcement is about, Perspec System Verifier does precisely that.

Our team and I will provide more details in the months to come. Also, at the upcoming DVCon 2015 in San Jose, STMicroelectronics will present a related paper called, “Automated Test Generation to Verify IP Modified for System Level Power Management.” Finally, Mike Stellfox, our verification fellow, Larry Melling, and I will give a tutorial at DVCon – “Verification Solutions for ARM v7/v8 Based Systems on Chips” – that will cover, besides other technologies, Perspect System Verifier in more detail.

Leave a Reply

(Note: This name will be displayed publicly)