Training The Next Gen For Low Power

While there is impressive research coming out of universities today, more could be done to advance power management in research activities.

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Reflecting on my time at this year’s Design Automation Conference, I am quickly reminded that I work in the most fascinating industry I can think of. Having the opportunity to discuss deep technical low power design issues, forward-looking challenges as well as the business implications face to face with thought leaders is inspiring and invigorating. With the amount of brain power filling Moscone Center this week, there should be a glow emanating from the convention center.

On the first day, I was intrigued by a Pavilion Panel on low power as I heard about the techniques needed at 28nm and 20nm such as sub-clock power gating, clock power gate structures, and adaptive body biasing, among others. Also, Bob Patti at Tezzaron reminded us that the biggest power savings are achieved in the architecture. He should know: Tezzaron builds multicore 3D processors. The panel highlighted the fact that power analysis today is done too late to be of any use, but new technologies are becoming available that allow for data mining of the physical design to improve RTL and achieve more power optimization than is possible at the gate level.

While soaking in the power talk, I wondered if all of this new and exciting stuff is being taught in the universities today and asked Dr. J. Bhasker, a prolific author and he believes more could be done to teach the basics, which led him to co-author a new book on the topic.

Further, he has observed that much of the research done at the world’s leading EE universities is focused on very advanced and sometimes esoteric techniques, but there is still much that could be learned from a close look at power management.

–Ann Steffora Mutschler