TSMC OIP, Vertical Integration And The Power of Ecosystems

After several attempts I’ve made it – my presentation at the TSMC OIP Ecosystem Forum was accepted this year. You may ask, what does a front-end guy like me do at a technology implementation forum like TSMC OIP? And why is he excited about it? The short answer is that it brings back my past. I am excited about how the front-end flows and implementation flows get connected in a closer way. It’s also very instructive for me to experience the sheer power of ecosystems.

Well, as to bringing back the past, I actually started my career in full custom layout. My first chip development was in the area of motion estimation for HDTV, and as described in “A Single Chip Solution for a High Speed 128-Point Radix-Two FFT Calculation,” memory was a key issue at the time. To save memory, I designed a three-transistor dynamic memory cell, which was later implemented in 0.8 micron technology as part of the chip. The chip was part of a bigger chipset—six of them were connected on a board—to eventually provide motion vectors into a hardware-based encoder for HDTV. These were the days prior to logic synthesis, and I remember working all the way from the transistor SPICE level though gates and RTL and even the transaction level.

The core of my presentation at the TSMC OIP event was about “vertical integration” as described in my 2016 Outlook blog, and I specifically outlined details of how our low-power optimization flow works. Users connect activity data collected in emulation with the technology information as it is captured in .lib technology files.

As a result, users can find the peak power and energy consumption across much longer runs, specifically in the context of software executing on the Palladium emulation environment at MHz speeds. This would not be feasible with classic RTL simulation that typically runs in the Hz or, at best, the low KHz range.

Just like my FFT chip was a part of a bigger system, representing Cadence as an EDA vendor made me feel like part of a very advanced, much bigger ecosystem. TSMC is at the center of a complex landscape of IP providers, EDA vendors, design center alliance members and value chain aggregators. It is very impressive and comprehensive, a true enabler for TSMC as also described in “The Keystone Advantage.”

Being part of an ecosystem of such size is an interesting experience, and as I described in “Game of Eco Systems” a while back, the race in the area of IoT is interesting. Softbank/ARM’s Dr. Dipesh Patel was actually keynoting at TSMC OIP and described the edge though hub to network and cloud IoT vision with the huge wave of IoT ahead of us. The other processor architectures – Intel, MIPS and PowerPC – are also still well in the race to enable IoT though, as are new players like the open RISC-V architecture. It is fascinating to watch.

Incidentally, ecosystem landscapes also overlap and merge. Navraj Nandra gave a very interesting presentation titled “Functional Safety and Reliability Reference Flow for Automotive Applications.” Referencing Intel’s acquisition of Yogitech, he showed a slide of how automotive and IoT worlds are merging and how the hardware requirements to enhance functional safety for IoT and automotive systems are really very similar. Case in point, I just ran across a very complex infographic by Spoke Intelligence showing the landscape for connected cars. According to Spoke, today the landscape comprises 242 companies, $38B in funding and a current valuation of $126B. And making Navraj’s point, 54 of the companies in that landscape are “Things” in the IoT sense.

TSMC OIP was a great event giving fundamental insight into the power of ecosystems. The vertical flow integration connecting traditionally disconnected flows – my presentation topic – is an important part of it.