Turducken Lessons

What you can learn about complex ASICs from a weird holiday food combination.

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By Doug Ridge
So with the U.S. holiday season just having passed, it seemed that the topic of discussion and of many a holiday feast was the now infamous turducken. Yes, the somewhat crazy idea of stuffing a deboned chicken with seasoned stuffing and then stuffing that inside a deboned duck, which is itself stuffed inside a deboned turkey, was making its way into homes across at least North America and perhaps even further afield, leaving many a person, well…stuffed. Now that the turducken has settled, I hear you ask, “It may be an interesting holiday food fad, but how does it relate to ASICs?”

If we consider the structure of an ASIC from inside to out, then naturally the IP forms the seasoned stuffing. The ASIC die is therefore the chicken; the substrate becomes the duck; and finally the package ends up as the turkey. While in food terms the challenge of the turducken is in making sure it gets cooked the whole way through and to perfection, the challenge of the ASIC is making sure that everything comes together perfectly and works to spec. Checking that the strange beast of the turducken is cooked correctly and that the flavors blend together perfectly when eaten is similar to being able to test the ASIC to ensure performance to spec once it is integrated into the final product. I hadn’t thought much about the overall solution or covered them in previous blogs, but after being involved in a number of projects where test had come up many a time in discussions, the whole solution became something of interest in terms of how IP plays into it.

Even at the macro scale of the overall chip, the smallest ingredients matter to a large degree. IP becomes not only about the cost, size and performance of the individual blocks, but how they fit into the ASIC along with the other IP and how the overall device becomes testable in a way conceived by the designers from the project concept. DFT, or design for test, has become increasingly important as the internals of the design become more deeply embedded with, well, the internals of the design.

Being able to get to these parts and test them is something that needs to be considered from the concept and throughout the design right up to package level. Scan chains at the individual IP level can end up costly at the chip level in terms of how they fit in with the overall device testability. Longer time on the tester or having to use a more expensive tester can produce unforeseen costs. In many cases we end up having to rethink test plans and add to test costs due to the microeconomics of the design, much like the wrong stuffing in our turducken can cause a complete change in the end result.

Fortunately with current designs we are able to test much more of the design through scan chains, BIST and MBIST and by using tools such as Synopsys’ Tetramax or Mentor Graphic’s TestKompress. Close cooperation with IP vendors to understand the built-in test that they have included in their IP also helps ensure good fault coverage. With respect to memory testing, it has become much simpler recently and is now considered straightforward. But more complex IP, such as SerDes IP, is becoming increasingly complex in the test environment due to the need to test not only through loopback testing, but also to test functionality and to test that at speed. Functional testing of this IP requires more complex test structures with active components leading to more costly and complex test boards. To understand the economics, logic and functional requirements and options, the designer must work closely with not only the IP vendor but also with the end customer and have a good knowledge of tools and testers available to him, including their limitations.

So unlike the turducken where the chef keeps his fingers crossed in the hope that things turn out to plan and can only probe the temperature, the ability to test the complex ASIC begins from the concept stage and enables the design, manufacture and test of the end product to happen seamlessly. You might enjoy your turducken, but having your ASIC work first time is much more satisfying.

–Doug Ridge is strategic source manager at eSilicon.


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