Ubiquitous Trend In Design for Power (DFP) For IP And SoCs

Excessive power consumption is a problem everyone needs to bring under control.

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Semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products. Analyzing and reducing power across the board in all market segments has become a key requirement and a differentiator, especially over last 8 to 10 years for IP and IP-based SoC designers. Many products live and die due to their green footprint. Today’s energy-efficient applications are ubiquitous in almost every market segment ranging from mobile, compute server farms, storage devices to Internet of Things (IoT) applications like wearables, autonomous cars to healthcare. Dynamic power consumed by SoCs continues to rise in spite of strides made in reducing the static power consumption in advanced technology nodes.

There are many reasons for dynamic power consumption waste — redundant data signal activity when clocks are shut off, excessive margin in the library characterization data leading to inefficient implementation, large active logic cones feeding deselected mux inputs, lack of sleep or standby mode for analog circuits, and even insufficient software-driven controls to shut down portions of the design. Another aspect is the memory sub-system organization. Once the amount of memory required is known, how should it be partitioned? What types of memories should be used? How often do they need to be accessed? All of these issues greatly affect power consumption. Therefore, design must perform power-performance-area tradeoffs for various alternative architectures to make an informed decision.

It is clear that excessive power consumption is an “equal opportunity problem”, and a variety of design techniques, tools, and methodologies must be employed to achieve low power design.

The phenomenal growth in device integration and advanced low-power design increases the complexity of ensuring power and thermal integrity of a techniques such as clock-gating and power-gating result in large power gradients surges that can cause the power delivery network (PDN) to fail. PDN integrity on a chip, on the board and in the system must be preserved under a multitude of complex functional scenarios that span the entire chip design.

Let’s look at the governing equation for dynamic power consumption:

Dynamic power consumed  Screen Shot 2014-10-08 at 3.11.06 PM , where
Screen Shot 2014-10-08 at 3.13.12 PM = Activity factor
Screen Shot 2014-10-08 at 3.11.40 PM = Switched capacitance
V = Supply voltage of the domain
f= Clock frequency

This equation must be addressed at all Levels of design abstraction to reduce dynamic power consumption. Scaling threshold voltage is addressed mainly to reduce static power consumption.

More than 20 power reduction techniques must be employed during all the design phases from system level, RTL to gate level sign-off to model and analyze power consumption, providing methodologies to meet power budgets, while managing tradeoffs associated with each technique that will be used throughout the design flow. Unfortunately there is no single silver bullet to reduce power.

Simultaneous optimization across the system, board, package and the chip is essential for successful power reduction, signal bandwidth performance and cost management. As chips migrate to sub-20 nanometer (nm) process nodes and use stacked-die technologies, the ability to model and accurately predict the power/ground noise and its impact on the chip is critical for the success of advanced low-power designs and associated systems.

When designing a chip to meet power budget requirements, the engineer will need to validate for a wide variety of operating conditions. For example, a chip for a smart phone must be tested to ensure that it meets power budget requirements in standby, dormant, charging, and shutdown modes. A comprehensive power budgeting solution provides accurate power value for numerous operating modes.

Several industry leaders are also discussing the emerging standard called High Level Power Model (HLPM) through working groups within Si2. The industry must rally around one standard to avoid the divergence which we saw in the early years of CPF and UPF. End users, foundries and EDA vendors must collaborate to create effective methodology for ultra low-power design flows specifically from system to final GDSII sign-off.

This systematic approach to power budgeting will ensure smooth ultra-low power IP and IP-based SoC design process and prevents highly iterative, costly, and error prone loops.