How to improve cycle count and energy consumption using processor acceleration.
This paper presents a case study on computing the 3D orientation of a device by means of a 9D fusion algorithm. The focus is on optimizing the fusion algorithm for execution on the DesignWare Sensor IP Subsystem. Performance measurements show the benefits of using ARC Processor EXtension (APEX) accelerators, which improve both cycle count and energy consumption in comparison to other commercial processors by a factor of 6-25.
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Steps are being taken to minimize problems, but they will take years to implement.
But that doesn’t mean it’s going to be mainstream anytime soon.
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New capacity planned for 2024, but production will depend on equipment availability.
Number of options is growing, but so is the list of tradeoffs.
Increased transistor density and utilization are creating memory performance issues.
The industry reached an inflection point where analog is getting a fresh look, but digital will not cede ground readily.
Disaggregation and the wind-down of Moore’s Law have changed everything.
FPGAs, CPUs, and equipment receive funding in China; 98 startups raise over $2 billion.
But that doesn’t mean it’s going to be mainstream anytime soon.
Funding rolls in for photonics and batteries; 88 startups raise $1.3B.
Why UCIe is so important for heterogeneous integration.
Analog foundry expansion; EDA investments; 112 startups raise over $2.6B.
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