Unified Design Flows Require New Skill Sets

By Pallab Chatterjee
With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools.

These new tools were created to address the need for simultaneous Multi-Corner Multi-Mode (MCMM) design analysis that is part of modern 65nm and below SoCs. While the automation helps unify the design task, it also requires a major restructuring of the design skills of the operator.

The typical design flow, in use since the early 1980s, has been a logic and functional design team that creates a gate-level design with timing constraints. This design then goes to a physical design team, which with an understanding of the process and use models for the physical view of the IP being used, starts with placement of the design. Using the same physical design team, the routing and buffer insertion/clock tree creation is done.

If there are failures in timing closure, then the logic design teams are usually re-engaged to verify that the physical-based re-synthesis of the local logic is done correctly, the test is re-inserted, and the functional verification is still valid and has been re-verified. The design then goes to a physical verification (PV) specialist who has access to the full process design rules, who fixes DRC and LVS errors, as well as the ERC, RCx and DFM rules. The last step requires a layout designer and masking engineer, who performs the final assembly with analog and I/Os not part of the P&R flow and perform the release to masking prep. This stage includes the CMP, OPC and other rule repairs.

The design tasks are split in responsibility due to the large number of rules and guidelines that are required to be implemented as well as understood so the correct tradeoffs can be selected. While the count of DRC rules has been well tracked as processes have progressed from the 250nm world down to the 32/28nm region, the entire mass of constraints has not been an area of focus. A typical PV run-set for 32/28nm is about 2,000-plus rules. With the addition of the masking, OPC, CMP and electrical application rules, that adds an additional 1,000 rules, bringing the total to 3,000-plus.

These “build rules” are applied to a typical netlist as a combination of three forms: SPICE/CDL, Verilog, and RTL, which describes the typical 250 million devices that make up the chip for the LVS description. To oversee such a design, there are also several hundred thousand to several million gates of test logic that have to be incorporated as part of the non-critical path timing in the design, but as part of the simultaneous switching power constraints for the design. Finally, there has to be final compatibility with logic verification and functional verification for the design, which in current design may comprise 70% or more of the total design task, and consist of millions of lines of code.

The new tools take these conditions, and automate the loading of the constraints and rules for multiple design corners, and can even make decisions about how to implement repairs to meet the goal. The assumption is that the operator (engineer or engineering from multiple disciplines) is overseeing the tool and making sure that the decisions it is making are appropriate for the design and do not alter the tradeoffs in performance, risk, power, yield and signal integrity that are part of the design and have not been captured in constraint metrics.

The tools do not remove the requirements for all of the skill sets and people needed to do a design. They merely automate some aspects of the design flow so these engineers can address the magnitude of the current designs. The design tools, in contrast, now require senior level operators who are trained on an interdisciplinary level to be able to adjust and select tradeoffs that affect many portions of the flow from a single “selection of correction” option.