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Advances In EM Analysis And Design Flows For RF System Development


With the move toward higher frequencies and component densities, RF/mixed signal PCB systems and heterogeneous system-in-package (SiP) technologies are increasingly susceptible to delayed product development turnaround times that threaten delivery schedules. These delays often occur late in development during integration when components that met the design specifications fail to achieve the req... » read more

Hyper-Convergence Is The New Normal For Digital Implementation


The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible


We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

Over-Design, Under-Design Impacts Verification


Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

Consolidating RF Flow for High-Frequency Product Design


Design flows are currently fragmented due to the use of poorly connected EDA tools for various design tasks. Fragmented flows are unable to meet new challenges such as increased system and circuit complexity, stricter bandwidth requirements, smaller device sizes, and changing packaging needs. In this white paper, we look at how the Cadence Virtuoso RF Solution provides a single, well-integrated... » read more

Methodologies And Flows In A Rapidly Changing Market


A growing push toward more heterogeneity and customization in chip design is creating havoc across the global supply chain, which until a couple years ago was highly organized and extremely predictable. While existing tools still work well enough, no one has yet figured out the most efficient way to use them in a variety of new applications. Technology is still being developed in those marke... » read more

One On One: John Lee


John Lee, general manager and vice president of Ansys—and the former CEO of data analytics firm Gear Design Solutions, which Ansys acquired in September—sat down with Semiconductor Engineering to talk about how big data techniques can be used in semiconductor and system design. What follows are excerpts of that conversation. SE: What's your goal now that Gear has been acquired by [getent... » read more

Unified Design Flows Require New Skill Sets


By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more