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Customer-Developed, Hyper-Convergent Design Flows Are Now Possible

Creating unique design flows based on a unified, shared data model.

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We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonly referred to as shift-left. Traditionally, this technique requires the lengthy process of transferring specific technology pieces across tools to fulfill only a certain flow requirement. While useful, each customer’s design flow is unique, and applying the same flow limits its effectiveness. The ability for design teams to create their own custom, hyper-convergent design flow easily, based on a unified, shared data model has been out of reach. Until now.

The foundation
The path to customer-developed, hyper-convergent design flows began in 2018 with the announcement of the Synopsys Fusion Compiler RTL-to-GDSII solution.  With this introduction, a truly integrated RTL-to-GDSII product architected with a single, scalable data model became available for the first time. The implementation engines were written from the ground-up to deliver a true RTL-to-GDSII design flow. The best optimization engines were consolidated into a unified super engine. Moreover, trusted industry golden signoff engines were integrated with the common data model to deliver a design flow that is signoff-correlated by construction. These proven engines could now be directly accessed anywhere in the Fusion Compiler flow.

This RTL-to-GDSII solution paved the way for high productivity and flexibility for our customers. 20 percent better quality of results and 2X faster time-to-results were reported, but this was only the beginning. Thanks to the single, scalable data model, a unified shell was now possible, one that controls all aspects of the RTL-to-GDSII process. It was this series of innovations that created the perfect storm for customer innovation.  Now, for the first time, customers could create their own hyper-convergent design flow based on their specific needs. The results have been quite exciting.

The emergence of customer-developed, hyper-convergent design flows
Change is never easy. Stepping away from a tried-and-true way of doing anything is difficult. Chip design flows certainly fit this pattern. Design teams develop scripts, verify technology files, and validate results over years for highly complex design tasks. Moving to something new, even if it holds the promise of dramatic improvements and competitive advantage, is a gradual and careful process.

To begin with, customers started moving existing stitched-together design flows onto the singular platform to gain immediate software architectural-based PPA and efficiency benefits.

As the early wave of customers settled into production deployment, several were ready to open the door on a new chapter in chip design. One where the customer is now in control of how to harness design flow convergence to build the best chip possible. What follows are some examples of what true customer innovation looks like.

Unified physical synthesis for improved physical correlation 
A mobile semiconductor company wanted to unify synthesis and placement, including auto-floorplanning. Using the Fusion Compiler unified shell, they created a unified physical synthesis flow with the goals of:

  • Better PPA
  • Faster runtime
  • Improved correlation

The figure below summarizes the results achieved on an Arm Cortex-A73 design. Substantial improvements across the board.

Pre-synthesis design planning for improved convergence
A high-performance computing company wanted to pre-route and buffer critical nets over RAMs in pre-synthesis. The goals here were:

  • Better timing and improved congestion for critical nets
  • Avoid the need to stitch multiple tools/shells

Again, using the Fusion Compiler unified shell this flow was developed. The figure below summarizes their results. Another case of substantial gains through methodology innovation.

Pre-placement clock synthesis for improved timing correlation
A datacenter networking company wanted to create early H-tree clock trunks prior to placement. The goals here were:

  • Better PPA
  • Improved timing convergence

The figure below summarizes their results using the Fusion Compiler unified shell. Another win with 50% better total negative slack (TNS).

Placement-based logic optimization for improved PPA
A mobile GPU company wanted to perform logic restructuring optimization during placement. The goals here were:

  • Better quality of results, faster runtime
  • Improved design input for clock tree synthesis

The figure below summarizes their results. Again, significant improvements across the board. All goals were achieved.

What’s next
Machine learning and prediction can bring significant benefits to a chip design flow. For example, Fusion Compiler uses machine prediction to speed up the path to the best optimization solution, and to prevent DRC/timing surprises downstream. Machine learning effectiveness is directly dependent on the quality of the training data. In addition to the big data accumulated in previous design iterations or past projects, we have the opportunity to reinforce training data early in the flow, within the same run, on the current design revision, that will be extremely relevant for downstream operations.

We applaud the customer results presented here and are ready to help other customers move into the new world of customer-developed, hyper-convergent design flows. The freedom to innovate at the design flow level is now available to all customers. You can learn more about the Synopsys Fusion Compiler here.



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