Chinese EDA


If you saw this headline and thought you missed a press release, don't panic. China has not, at this point, announced to the world that it has a suite of EDA tools ready to roll. The rest of the world is content to look at the substandard attempts it have made so far and write them off as not being capable of developing competitive EDA software. But in all likelihood, given the current politica... » read more

Is Synthesis Still Process-Independent?


For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion. With the arrival of physical synthesis, physical effects could be taken into consideration in... » read more

IP Qualification During RTL Synthesis


By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

IP Qualification with Oasys-RTL


With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more