Using An Integrated Subsystem To Accelerate Data Fusion In Your SoC

The fusion of sensor data, voice, audio and biometrics is constantly increasing the processing requirements for applications in mobile, automotive and IoT markets. Next-generation digital sensors require higher bandwidths, and more advanced voice detection and speech recognition algorithms are driving the development of progressively more complex embedded ICs.

Sensor fusion to data fusion
The combining of basic sensor elements into a higher order function is called sensor fusion. For example, combining the input from an accelerometer, compass and gyroscope to track 3D motion is common in all modern smart phones. The number of systems incorporating sensor fusion technology continues to explode as semiconductor suppliers push to integrate multiple sensors into their devices.

Mobile application processors are an excellent example of the upward trend in sensor integration. To address the 10-15 sensors deployed in the average mobile connected product, the MIPI Alliance has released a new standard, I3C, defining a higher performance interface for sensor connectivity. The MIPI I3C standard incorporates characteristics of I²C, SPI and UART in a simple, high bandwidth, 2-wire interface (clock, data). It provides SPI performance with the simplicity (and backward compatibility) of I²C. Figures 1 and 2 show how integration of various sensors to a host processor can be simplified using I3C.

Figure 1: Typical sensor integration using traditional interfaces

Figure 2: Simplified sensor integration using I3C

In addition to sensor processing, today’s IoT applications demand even more integrated functionality, which requires support for voice and gesture recognition, audio playback and basic image detection. A higher level of DSP processing capability is needed to perform these functions, but at the same time it must be done with the lowest energy consumption possible. Data fusion has become a standard requirement in IoT edge devices addressing applications such as wearables, personal health and fitness devices, and wireless headsets and speakers.

The XY memory implementation of the DesignWare ARC EM9D and EM11D processors reduces overall energy consumption by allowing applications to move parallel data in and out of memory (local X and Y) per clock cycle. This enables a higher (sustained) MAC/cycle throughput providing higher DSP performance for applications such as audio playback and gesture recognition by reducing the number of overall clock cycles it requires to perform these functions. Figure 3 highlights the advantages of using XY memory architectures as you move from more RISC-intensive applications to those requiring more signal processing capability.

Figure 3: Energy consumption comparison of IoT voice/audio functions

Advantages of an integrated subsystem
The advantages of increased integration can differentiate a silicon vendor’s device. A typical “integrated” solution today involves incorporating the various data interfaces into a microcontroller-like architecture. An integrated IP subsystem offers distinct advantages in easing integration effort while reducing on-chip latency and energy consumption compared to typical bus-based systems.

The DesignWare ARC Data Fusion Subsystem leverages an integrated ARC EM processor, tightly coupled peripherals, hardware accelerators and software to address the fast-growing IoT edge device market – specifically targeting “always-on” applications requiring a robust level of DSP performance to process functions such as complex sensor fusion, voice and gesture recognition, image detection and audio playback while adhering to the constrained power envelope of a battery-operated device.

The ARC Data Fusion IP Subsystem (Figure 4) is designed to efficiently process data from numerous digital and analog sensors, either as the main processing element in an MCU, or as an offload engine for the host processor in a larger SoC. The fully configurable IP subsystem includes an ARC EM5D, EM7D, EM9D or EM11D processor. This family of low-power cores combines RISC and DSP instructions and hardware to manage the extensive processing required by advanced data fusion algorithms and to improve performance for a range of “IoT audio” formats including MP3, SBC, OPUS and AAC LC.

To ease software development, the subsystem includes software drivers and a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/interpolation and complex math operations. Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption.

The integrated IP subsystem with pre-verified hardware and software allows designers to incorporate and efficiently process data from the increasingly wide array of fusion elements found in low power systems.

Figure 4: Synopsys ARC Data Fusion IP Subsystem with new interface options

Summary
The rapidly expanding IoT edge device market continues to push boundaries on integration, cost, and performance. “Always-on” data fusion has extended to include higher performance sensors, voice, speech and audio functionality.

The increased bandwidth demands drive both RISC and DSP performance requirements. An integrated, pre-verified subsystem providing a wide array of sensor interfaces, including I3C, and advanced audio support allow SoC design teams to realize significant gains in overall performance, while reducing software footprint, silicon area and energy consumption in embedded IoT systems.