Verification Of Multi-Clock Designs: The Bigger Picture

Well-designed clock architectures have appropriate synchronization and the associated constraints are complete and correct.


Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this is further complicated by multiple modes of operation and the associated range of clocking scenarios.

This leads to ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. In this environment, designers, chip integrators and back end engineers must ensure the integrity of the clock architecture, and the integrity of its associated timing constraints.

A well-designed clock architecture (including asynchronous interfaces) will address two key issues:

  1. It will have appropriate synchronization schemes in place at all necessary points, and
  1. the associated constraints (clock to clock false paths for example) will be both complete and correct

According to a recent IBS report – “Because it is not as easy to predict whether designs will operate as expected and reach production volumes as feature dimensions shrink and designs become more complex, a number of IC vendors, their customers, and supply chain partners are facing major financial problems. Providing tools that improve predictability can have large financial benefits to a range of companies” [1].

This White Paper outlines a holistic approach to resolving these issues, by exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk.

To download this white paper, click here.

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