Vtech: Bus Performance, FPGA Debug

It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short. If you do a search for them, you will probably find a company that sells baby monitors and kids toys. This is not that company. So, let’s make sure you have the right web address to start with https://vtech-usa.com/ or https://vtech-inc.co.jp/

Most EDA companies get established in one of three ways. The most common these days is for an existing EDA company to be acquired by one of the big three. The founders subsequently leave and start a new company with a new idea. The second, which is not as common today, is for a piece of university research to be commercialized. The third is for a consulting or systems company to commercialize technology that they developed to help them succeed in their marketplace. That is the case with Vtech.

Originally founded in Japan in 2003, Vtech now employs about 100 people, mainly engineers who reside in Japan, Manila and now San Jose. Semiconductor Engineering spoke with Hideto Takeuchi, CEO and founder of Vtech.

SE: What was the problem you set out to solve?
Takeuchi: I was chief of sales and marketing of an emulator team in 1999 and I could see that verification time was increasing faster than RTL coding in SoC development. This was due to SoC designs getting larger, with a lot of functions and IPs for many kinds of applications. The market needed to shorten verification time with high-level verification techniques. That is why we founded Vtech in 2003 with a focus on verification technology. We initially found a market where clients needed help with their design verification. I also thought that Vtech should develop its own EDA tools and we saw the need for a bus performance analysis and FPGA debug. These were both useful for our clients and now we are releasing them as EDA tools.

SE: Tell me about the bus performance monitor.
Takeuchi: This is a performance monitor for AXI. Typically, there are many devices on an AXI bus, such as CPUs, peripherals, video subsystem, DDR controllers. Many of these systems are built using IPs and there are complex interactions between the components. Performance is a very critical aspect of these systems, and yet the major EDA vendors do not address this issue. We have been involved in multiple SoC development projects where performance verification is performed using logic simulators. We often found that systems do not deliver the expected performance in the actual chip. In addition, there was no easy-to-use tool for performance analysis on actual devices. So, we developed VARON, a bus performance verification tool that is used by incorporating it into actual chips. After the initial version of the product, we learned a couple of things. First, they wanted to use it with hardware emulators and second, they wanted both the numerical value of transfer performance, and they also needed features that help them analyze transfer bottlenecks. To realize this, we have developed version 2.0 and that is what we are shipping today.

SE: What kinds of problems does this allow the use to see?
Takeuchi: The software provides many types of performance charts for each layer of the bus interconnect system. Each of these can make certain types of problem become very clear, such as showing latency by port, timing of transactions on ports as well as more typical charts that might show when the bus was idle or the minimum, average or maximum cycles over time per port. Out of range thresholds can also be set that will immediately draw attention to problematic activity.

SE: What about the FPGA debugging tool?
Takeuchi: VSTAR came from our experience of debugging FPGA SoCs. On several projects we needed to investigate how access on the bus was executed starting from the time of an interrupt, and we spent a lot of time analyzing it. The challenge is that the system operates at the millisecond timeframe because it is controlled by software, while the hardware operates at tens to hundreds of nanoseconds. Due to this gap, traditional on-chip logic analyzers have a narrow observable time range, making them unsuitable for this type of debug. That was the motivation behind the development of VSTAR, which enables system-level debugging. To expand the observable time range, systems have to allocate a huge storage space and record data at high speed, but we chose a different approach for VSTAR. Our technology observes signal transitions in real-time and automatically extracts the rules for signal sequences. We have realized this as an embedded verification IP to the design under verification. On top of that, we have developed a system-level debugging tool that can monitor the operation of the system for several days, and detect malfunctions of the design, not knowing when it will occur, and automatically acquire the detailed transitions of signal states.