Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA

By Nayan Gaywala - 31 Oct, 2024 - Comments: 0

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

Defining The Chiplet Socket

By Brian Bailey - 29 Aug, 2024 - Comments: 0

Experts At The Table: The semiconductor industry has been buzzing with the possibilities surrounding chiplets, but so far this packaging technology has been confined to large semiconductor companies that are vertically integrated. The industry has been attempting to open this up to a broader group of people. To work out what this means for chiplets, and what standardization will be required, Se... » read more

Design Complexity In The Golden Age Of Semiconductors

By Frank Schirrmeister - 24 Aug, 2023 - Comments: 0

While writing last month's blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020 or earlier, but I was too close to the deadline to sit down and make orderly updates to some of the charts. Working day-to-day in the area of SoC integration and networks-on-chips (NoCs), the classic chart based on Karl Rupp's now 50 years of processor data that overlay... » read more

What Does 2023 Have In Store For Chip Design?

By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Is UCIe Really Universal?

By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

High-Level Synthesis For RISC-V

By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Vtech: Bus Performance, FPGA Debug

By Brian Bailey - 15 Jul, 2020 - Comments: 0

It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short. If you do a search for them, you will probably find a company that sells baby monitors and kids toys. This is not that company. So, let's make sure you have the right web address to start with https://vtech-usa.com/ or https://vtech-inc... » read more

Mixing Interface Protocols

By Ann Mutschler - 21 Dec, 2017 - Comments: 0

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

Supporting CPUs Plus FPGAs

By Brian Bailey - 11 Apr, 2017 - Comments: 5

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Correlating Software Execution With Switching Activity To Save Power In SoC Designs

By Russell Klein - 09 Mar, 2017 - Comments: 0

There is probably no more pointless waste of energy than lighting and heating a room that is empty. The obvious optimization: notice that no one is there and turn off the lights. It works the same on an SoC or embedded system. To save energy, system developers are adding the ability turn off the parts of the system that are not being used. Big energy savings but with no compromise to functional... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.