Video Compression And Forward Error Correction On Display Interfaces

To wrap up our recent series of articles on VESA video compression codecs, this month we will look at the use of video compression on digital display interfaces, using the DisplayPort 1.4 standard as an example.

DisplayPort (DP) 1.4 was released in 2016, and this was the first display interface standard for external displays to include support for VESA Display Stream Compression (DSC), a visually lossless, low latency compression algorithm that increases the DisplayPort data transfer capacity without changing the link speed.

DisplayPort 1.4 uses different fixed link speeds, up to 8.1Gbps (called HBR3). Using DSC with HBR3 transmission rates, DisplayPort 1.4 can support 8K UHD (7680×4320) at 60 Hz with 10-bit color and HDR. The overall takeaway is that DisplayPort is much more powerful with DSC than without; it enables higher resolution and refresh rates for many different types of DisplayPort applications including monitors, hubs, and TVs.

As DP 1.4 makes use of coaxial cables, bit errors in transmission are inherently present. A bit in error when using a DP 1.4 cable with uncompressed video has a very limited impact (1 pixel for 1/60 second) and this would not be noticed by users. However, it’s a different story when DP is carrying compressed video streams. The effect of bit errors on a compressed video stream are far more noticeable and not something you want to see when you are using your computer! Therefore, the DisplayPort standard specifies the mandatory use of Forward Error Correction (FEC) when DSC is activated.

FEC has been in use for many years now in everything from satellite transmission to mobile phones. It is a technique used for controlling errors in data transmission over noisy communication channels. The general idea is that additional information (redundancy or parity) is added to the data to detect and correct errors. DisplayPort specifies the use of a particular type of FEC code called Reed-Solomon, or more precisely RS(254,250). FEC adds redundancy to the information being transmitted through additional bits in the bitstream. The receiver side uses the redundant information to determine which bits are corrupted, and how to correct them.

Time to dive into some good old math for a moment! Without FEC, DP 1.4 has a bit error rate (BER) of 10^-9. The BER is the probability that a given bit will be corrupted. At 1080p resolution (1.58Gbps), we would expect to see a bit error every 1.58 seconds, so very often. With the use of FEC, the BER is 10^–18. At the same resolution, we would expect a bit error every 50 years! The bit error rate is, therefore, significantly reduced using FEC; it ensures a glitch-free visual experience for end users, while enabling manufacturers to take advantage of DSC to achieve higher resolutions and refresh rates.

DSC and FEC with DisplayPort 1.4 is just one example of the use of video compression over a display interface. HDMI 2.1, released in 2017, also specifies the use of FEC when DSC is used. VESA DSC can be used for HDMI 2.1 applications to achieve display resolutions such as 8K60, 8K120, and even 10K120! And DisplayPort 2.0 continues to push up display resolutions even further, allowing for resolutions up to 16K with HDR.

Rambus offers silicon-proven VESA DSC encoder and decoder IP cores, as well as Reed-Solomon FEC IP cores for both DisplayPort 1.4 and HDMI 2.1. An ASIL-B ready DisplayPort 1.4 FEC IP core for safety-critical automotive applications is also available.

Additional resource:

Rambus VESA DSC & FEC IP Cores