Waiting for Porous Low-k

Increased leakage and dielectric constant increase due to plasma damage and post-etch cleaning remain challenging.


I’m working on a longer article on low-k dielectric integration, but in the meantime I wanted to pass along an observation from Joubert Olivier of LTM-CNRS, in his presentation at the Materials Research Society Spring Meeting.

Asked about the prospects for low-k integration, he reminded the audience that even if an integration scheme is able to achieve good selectivity between the hard mask and the dielectric, and produce good sidewall profiles without pattern collapse, and prevent redeposition of etch by-products — all of which are significant challenges in themselves — even if all of these goals are achieved, the industry will still have to deal with the fundamental problems of increased leakage and dielectric constant increase due to plasma damage and post-etch cleaning.

None of these problems are new. The semiconductor industry has been struggling with them since the late 1990s, when porous dielectrics first began to appear in technology roadmaps. The lack of clear solutions more than ten years later prompted Olivier to suggest that maybe it’s time for a new strategy.

Other speakers at the MRS meeting suggested some possible alternatives. Sven Zimmerman of Fraunhofer ENAS, working in collaboration with Global Foundries, suggested a less damaging patterning regime based on a combination of CF4 etch chemistry, cleaning solutions optimized for the specific plasma chemistry, and a surface repair process. Theo Frot and a team at IBM suggested infiltrating a polymer into the dielectric pores to add mechanical support during the etch process, then removing it to restore the desired structure. Results were promising, but these ideas are still at the laboratory stage. For manufacturing, porous low-k dielectric integration is already running years behind schedule.

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