Waste Not, Want Not

How to debug your design for power.


Power is the new timing …. performance per watt … low-power design … power performance trade-offs … the list of terms goes on and on, but there is no denying that power has now become the primary design objective.

So what does it really take to manage power in a modern system-on-a-chip (SoC) design? Power is an “equal opportunity problem,” and all can contribute to the solution. What is really required to manage power is a design methodology that treats power seriously for every step of the flow, so that power is no longer an afterthought. Nor is it something that can be thrown over the wall from the front-end to the back-end.

Best practices dictate that power should be considered very early in the design process to enable power-driven design decisions. Once the hardware/software partitioning and overall SoC architecture has been decided, hardware must be designed to meet the target performance, power, and area (or cost) objectives. Hardware design at the Register Transfer Language (RTL) level of abstraction must depend on predictable, consistent, and accurate RTL power analysis tools to have a chance at meeting power targets, because by the time the design is synthesized from RTL to gates and the gate-level power analysis is done, going back to RTL is time-consuming and counter-productive.

Accurate RTL power analysis tools enable designers to have a solid estimate of power consumption early in the design process. But there is another very good reason to do early analysis—finding ways to reduce wasted power in the design! Consider the design shown in Figure 1.




Here, the DATA_OUT output of the block on the left is not active in the mode defined as!(TRANSMIT|RST), but the clock to the downstream FIR filters is free-running. However, the design is functionally correct: when DATA_OUT is not active, none of the filter outputs are active either. This is an example of redundant clock activity—the clock to the filter can be gated using (TRANSMIT|RST), thus saving a large amount of power.

The opposite of the power consumption bug described above—a redundant data condition—is also possible: a situation where data signals are active while clocks are shut off can also waste power. The relationship between clock and data activity is therefore key to reducing wasted power in the design and eliminating “power consumption bugs” – those wasted power conditions that are otherwise functionally correct. A simple “power debug quick start,” as shown in Figure 2 below, can be an effective guide for all designers to become adept at reducing or eliminating wasted power.



Modern RTL power analysis tools can trace upstream and downstream cones of logic, identify clock gating enable conditions, display input and output signal frequencies, track low data activity vs. high clock frequency, and provide other useful information.

Waste not, want not: RTL designers must take advantage of these capabilities to deliver power-efficient RTL source code and not expect the downstream design flow to auto-magically fix their power bugs.

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