Week In Review: Design, Low Power

Si2’s Unified Power Model has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018. UPM/IEEE 2416-2019 provides a set of power modeling semantics enabling system designers to model entire systems with flexibility. It supports power modeling from abstract design description to gate level implementation, providing data consistency from earliest architectural explorations to final power verification. “The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” said Nagu Dhanwada of IBM and chair of the IEEE 2416 and Si2 UPM Working Groups.

Avery Design Systems launched two new verification tools for simulation, SimRegress and SimCompare. SimRegress provides the ability to capture and replay the simulation testbench stimulus without having to run the full testbench, supporting improved methods for 3rd party IP debug using tests directly from the customer SoC verification environment. SimCompare provides a smart diff feature between RTL and gate-level simulation, correlating RTL and gate-level signal names and transaction synchronization between the two simulations being compared. Both work with Synopsys’ Verdi and Cadence’s SimVision.

Vidatronic uncorked a new low dropout (LDO) voltage regulator IP core optimized for battery-powered devices where low power is critical and where size, output voltage accuracy, and output noise are of concern. The VLDS0300LS130 Power Quencher IP core is a low-power, fully-integrated LDO voltage regulator that achieves a low-noise output voltage without the use of external components. It can support input voltages from 2.5 to 6.0 V, output voltages from 1.2 to 5.5 V, and provides up to 300 mA of load current. It is available through the Samsung Advanced Foundry Ecosystem.

Samsung is using secure data exchange in Synopsys’ Yield Explorer to share data required for yield analysis, such as chip design, fab, and test, with its customers while maintaining the confidentiality of proprietary information from each party. Yield Explorer uses data from various sources with datamining and visualization techniques to identify dominant causes of yield loss.

Cadence’s digital full flow was certified for Samsung Foundry’s 5nm Low-Power Early (5LPE) process with EUV. The certification used the Arm Cortex-A53 and Cortex-A57 cores for the 5LPE process.

Synopsys updated its LucidShape CAA V5 Based software for optical simulations and analyses of automotive lighting products within the CATIA V5 environment. Updates include improvements to the surface sensor feature for analyses of illuminance and irradiance on curved surfaces, ray result filtering by surface, and new options in the Light Guide Design Module.

Events
ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

And Semiconductor Engineering now has an Events page for the industry. Check out upcoming conferences, including SEMICON West & ES Design West next week.