Week In Review: Design, Low Power

Dialog Semiconductor will acquire Adesto Technologies for $12.55 per share in cash, or for approximately $500 million enterprise value. Founded in 2006 and based in Santa Clara, CA, Adesto provides application-specific semiconductors, embedded systems, and specialty memory for IoT and industrial IoT applications. “This acquisition substantially enhances our position in the Industrial IoT market,” said Jalal Bagherli, CEO of Dialog. “Adesto’s established strength in connectivity solutions and highly optimized products for building and industrial automation perfectly complements and adds scale to our Industrial IoT portfolio from the recently acquired Creative Chips. Adesto’s deep customer relationships, comprehensive system expertise, and proprietary technology will deliver enhanced value for Dialog customers.” The deal is expected to close in the third quarter of 2020.

Synopsys finalized the acquisition of certain IP assets of Invecas. The acquisition adds to the company’s Logic Library, Embedded Memory, General Purpose I/O, Analog, and Interface IP portfolio. A team of physical design R&D engineers are also joining Synopsys. Invecas will retain its HDMI IP and ASIC Design Solutions. Terms of the deal were not disclosed.

Accellera formed a Functional Safety Working Group to create a standard that improves interoperability and traceability in the functional safety lifecycle, specifically targeting analysis, design, verification and implementation operations and related safety work products. “Our objective is to develop a standard which captures and propagates the functional safety intent. This helps to better integrate analysis methods such as FMEDA, DFA and FTA and to enable a functional safety-aware design and verification flow for electronic circuits and systems,” stated Alessandra Nardi, Functional Safety WG Chair. The group will initially focus its efforts on the development of a white paper to explain the motivation and possible directions in the creation of a functional safety standard, followed by a Language Reference Manual (LRM) that will provide the definition of the functional safety format.

Tools & IP
Imagination debuted its latest Bluetooth Low Energy (BLE) IP, supporting the latest Bluetooth SIG version 5.2 specification. iEB110 is a complete BLE solution, including RF, controller software and Bluetooth Low Energy host stack. It includes open-source Zephyr and Cordio host stacks, integrates with Imagination’s Wi-Fi IPs, and supports Bluetooth 5.2 features such as Angle of Arrival/Angle of Departure (AoA / AoD) allowing sub 1m location and tracking accuracy, LE long-range operation for extended indoor and outdoor coverage, and LE-2M PHY for higher throughput.

SmartDV introduced new DDR5 and LPDDR5 SDRAM controller IP offering low power and latency and reduced gate count for increased memory interface bandwidth. The IP targets multiple applications from high-performance computing to IoT and mobile. The DDR5 Controller Design IP Core supports the JESD79-5 Rev095 specification, while the LPDDR5 Controller Design IP core supports the JESD209-5 LPDDR5 specification. Both are compatible with DFI 5.0 and support a variety of host bust interfaces, including AHB, APB, OCP, TileLink, Wishbone, VCI and Avalon PLB. Additionally, SmartDV’s entire IP portfolio now supports the new MIPI I3C v1.1 utility and control bus specification. The MIPI I3C host controller interface (HCI) 1.1 draft spec is also supported.

Socionext uncorked Time-Sensitive Network (TSN) IP for FPGA and ASIC implementation. The IP provides true deterministic Ethernet for industrial applications and supports a 2-port daisy chain topology suitable for connecting industrial equipment, 1 Gbps high-speed operation, low latency less than 400 ns, and low jitter less than 0.1 µs. Provided is an FPGA evaluation board and start-up manual for IP implementation, as well as Linux open-source driver software.

GOWIN added support for Ubuntu to its GOWIN EDA FPGA development software to better integrate FPGA synthesis, place and route and bitstream generation into AI design and script work flows.

NanoLock Security and Adesto teamed up on flash-based embedded security and management solutions for low-density flash memory devices used in products such as smart meters, sensors and controllers. The combined solution provides a hardware root-of-trust in the device’s flash memory that blocks unauthorized modifications to prevent persistent control of the device.

AI
Eta Compute announced the first shipment of production silicon for its ECM3532 AI multicore processor for always-on embedded sensor applications. It uses the company’s Continuous Voltage Frequency Scaling (CVFS) with power consumption of microwatts for many sensing applications. It is based on Arm Cortex-M3 processor and includes flash memory, SRAM, I/O, peripherals and a machine learning software development platform.

XMOS uncorked xcore.ai, a crossover processor for the AIoT market targeted at real-time inferencing and decisioning at the edge, as well as signal processing, control and communications. It includes 16 real-time logical cores with support for scalar/float/vector instructions, DSP and ML capabilities, and support for 8-bit and binarized neural network inferences.

Deals
AMD adopted Synopsys’ Fusion Compiler RTL-to-GDSII product for its full-flow, digital-design implementation to be used in developing next-gen processors. The two companies also worked to optimize runtime acceleration benefits when deploying the Fusion Compiler RTL-to-GDSII product across servers powered by AMD EPYC processors. These advancements will be made available to all users in upcoming service packs.

Autotalks integrated Imagination’s CRF4600 radio frequency (RF) IP in its  PLUTON2 RFIC transceiver, which is part of Autotalks’ dual-mode solution for vehicle-to-vehicle (V2V) and vehicle-to-everything (V2X) communication. The IP is now in silicon and expected to be in production by 2021.

MikroElektronika’s new Click board uses Adesto’s FT 6050 Smart Transceiver SoC. The FT Click provides a universally accepted interface via a mikroBUS socket to embedded IoT ecosystems for prototyping of thousands of different IoT applications.

Numbers
Synopsys reported financial results for the first quarter of 2020 with revenue of $834.4 million, up 1.7% from the first quarter of last year. On a GAAP basis, income per share for Q1 2020 was $0.67, down 33.6% from $1.01 in Q1 2019. Non-GAAP income per share was $1.01, down 6.5% from $1.08 per share in the same quarter last year.

Events
Check out upcoming industry events and conferences: FPGA 2020 will be held Feb. 23-25 in Seaside, CA, and includes sessions on deep learning, architectures, tools, and security. Embedded World, the trade fair for embedded systems, will be held Feb. 25-27 in Nuremberg, Germany. DVCon is Mar. 2-5 in San Jose, CA; key topics include formal verification, Portable Stimulus, IP security, intelligent system design, AI and ML-focused verification, 5G verification, UVM strategies, power-aware design and hybrid verification. DATE 2020 will be held Mar. 9-13 in Grenoble, France and will feature special days focused on embedded AI, silicon photonics, and a special initiative on autonomous systems design. On April 3 from 11:30 am – 1:30 pm in Milpitas, CA, the ESD Alliance will host investor Jim Hogan and Simon Butler of Methodics for a lunchtime discussion about bootstrapping a startup and successfully creating a new market segment.