Week In Review: Design, Low Power

Ansys will acquire Lumerical, a developer of photonic design and simulation tools. “The potential of photonics in applications like 5G, IIoT and autonomous vehicles can only be realized by solving immense multiphysics device and system challenges,” said James Pond, co-CEO and CTO of Lumerical. “Together, Lumerical and Ansys are uniquely positioned to provide the necessary solutions, and customers of both companies will reap tremendous rewards from this dynamic acquisition.” Terms of the deal were not disclosed; it is expected to close in the second quarter of 2020.

Tessolve acquired Test & Verification Solutions (T&VS). Tessolve said the acquisition would bring its VLSI design to next level by bringing in an increased depth to front end design activities, catching design flaws ahead in the cycle, and reducing re-design costs. The company also points to a faster realization of turnkey products for its customers in the semiconductors and systems segment. Tessolve is part of the Hero Electronics group. Terms of the deal were not disclosed.

Tools & IP

CEVA uncorked its Gen4 CEVA-XC DSP. The new architecture targets complex parallel processing workloads required for 5G endpoints and Radio Access Networks, enterprise access points and other multigigabit low latency applications and enables two-times 8-way VLIW and up to 14,000 bits of data level parallelism.

Samsung adopted Synopsys’ IC Compiler II place-and-route solution for its next-generation 5nm mobile SoC production design. Samsung cited productivity boosts of up to five percent higher frequency, five percent lower leakage power and faster TAT.

UMC certified multiple Mentor products for its 22uLP (ultra Low Power) process technology, including Mentor’s Calibre, Analog FastSPICE, and Nitro-SoC digital design platform. The process targets set top box, digital TV, and surveillance applications, as well as battery-powered IoT and wearable devices.

Videos, Webinars and Conferences

New videos this week include Banking on FPGA Prototyping, Enterprise-Class DRAM Reliability, and Improving Circuit Reliability

Missed a conference or can’t travel? Check out upcoming webinars instead.