The Week In Review: Design

Functional safety suite; OVP models; high-end embedded ARC cores; 25G PHY; Samsung certifications.

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Tools

Startup Austemper Design unveiled a functional safety tool suite that includes safety analysis that applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates, tools to handle safety synthesis and augment design structures, and a parallel fault simulator with hybrid simulation capabilities. SystemVerilog and VHDL parsers from Verific serve as the front end.

Imperas Software released new Open Virtual Platforms (OVP) models for ARM, Imagination Technologies, RISC-V and Renesas processors, along with a new software release for virtual platforms which the company says provides a 2x performance improvement in simulation. A new modeling productivity tool also launched.

Mentor extended its test platform for Automotive Audio Bus (A2B) with a second-generation A2B Analyzer System, additional support for the Audio Stream Input/Output (ASIO) protocol, and plans for a new A2B passive bus monitoring product. New features include support for the latest AD242x family of transceivers from Analog Devices, including node simulation tools, A2B network configuration, and support for Slave-to-Slave node communication.

IP

Synopsys debuted new ARC HS4x and HS4xD processors. Targeted at high-performance embedded applications, the processors are available in single-, dual- and quad-core configurations and implement a dual-issue superscalar architecture that delivers up to 6000 DMIPS per core at 2.5 GHz while requiring 0.06mm2 of area and as little as 37 microwatts/MHz in typical 16nm finFET processes. The HS45D and HS47D also support more than 150 DSP-optimized instructions.

Synopsys launched multi-protocol 25G PHY IP for 7nm and 16nm finFET processes. It supports protocols including PCI Express 4.0, 25G Ethernet, SATA and Cache Coherent Interconnect for Accelerators (CCIX) and reduces power and area by more than 35% compared to the 16G PHY solution, the company says, by incorporating optional power management features such as I/O supply under drive and decision feedback equalization (DFE) bypass. The PHY targets high-performance computing applications including machine learning and artificial intelligence.

Samsung Certifications

Mentor extended Calibre for Samsung foundry customers, adding a tool to control access to a customer’s load-sharing facility, in which multiple remote machines can be used to run multiple tool flows in parallel, using either local CPU or LSF grid resources, as well as a single interface for the application of multiple DFM processes.

Additionally, an array of Mentor tools have been enabled for Samsung’s 8LPP process technology, and core components of the Calibre suite have been enabled for the Samsung 7LPP process.

Samsung 8LPP and 7LPP implementation flows have been fully enabled in Synopsys tools including IC Compiler II place and route and Design Compiler Graphical synthesis, and Synopsys Process Design Kits are now available for both processes. Additionally, Samsung certified Synopsys Custom Compiler for its 28FDS process.

Synopsys also launched an interface IP portfolio for Samsung 14LPP and 10LPP processes, including USB 3.1/3.0/2.0, PCI Express 4.0, HDMI 2.1/2.0, LPDDR4 and DDR4.

Cadence’s digital, signoff and custom/analog tools were enabled on Samsung’s 7LPP and 8LPP process technologies. They also were certified for the 28FDS process, including a 28nm FDS reference flow using a quad-core design with the ARM Cortex-A53 processor.

Ansys’ power integrity and electromigration solutions were enabled for Samsung’s 7LPP and 8LPP processes. Self-heat was also certified for 10nm chip technologies.