Whac-A-Mole Anyone?

Why SoC development increasingly looks like an old video game, but with much higher stakes.


By Mike Gianfagna
It started as an arcade game in 1976 (according to Wikipedia), so it’s been around for a while—longer than system-on-chip (SoC) design for sure. It’s essentially a game of futility. A mole pops up and you whack it down with a hammer, only to have another mole pop up elsewhere. Figuratively, you fix one problem and another one pops up. So what does all this have to do with SoC design? As it turns out, a lot.

Remember the good old days of 0.18 micron? You could close timing with simple models—and you could optimize power independently of timing. Once you got the chip to fit in the package, you were pretty much done. Small tweaks for performance or last-minute design changes were relatively easy to implement. Most optimization could be done single thread, one thing at a time. It was all relatively straightforward.


Fast forward to sub-45nm SoC design. The game is completely different, and it is a perfect example of the Whac-A-Mole concept applied to the high-stakes activity of SoC design. Now, all aspects of the chip are interrelated. If you reduce power, you can break clock synchronization. Whoops, up pops a mole. If you improve testability, this could increase power. Yikes, another mole … and you need to beat that one back. If you get too clever with your logic design, the chip just won’t route. But classic gamers and SoC designers aren’t alone. Earlier this week Reuters ran a story on “How to stop the Whac-a-Mole of insider trading.” Interesting.

In our world, the conversation centers more around power, performance and area—or “PPA” —optimization than whacking moles. The Holy Grail is the ability to simultaneously optimize power, performance and area as a holistic and deterministic process. This is a complex problem with high payoff—perfect for us EDA geeks to sink our teeth into. And chew on it we will. Watch for a wave of new tools and new methodologies aimed at taming this beast. We’re working on one, too, along with some pretty high-profile companies. Because Atrenta focuses on the early part of the design cycle, our solution will address ePPA. One guess what the “e” stands for.

Effectively managing the inter-related problems of power, performance and area optimization will pay off big for those who can get it right. Better performing designs, faster time to market and more predictable delivery schedule are just some of the benefits.

The Whac-A-Mole analogy does seem to make the point. If you think about the job description of a chip architect trying to balance all these aspects of the design, while drawing from a variety of semiconductor intellectual property sources (both inside their company and third party), another visual comes to mind, as well.


Customer reviews for Whac-A-Mole on Amazon.com include: “This Game Is A Blast! Highly Recommended,” “We all love this game,” and “Mindless fun.” I kind of feel the same way about ePPA, except perhaps for the “mindless” part.