What’s In The Package?

Advanced process technologies require IP characterization for packaging; where transistor performance bogs down.

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By Ann Steffora Mutschler
The growing market for smart mobile devices and high-performance processors requiring more than 2GHz of processing power is driving IP providers to do even more work to prepare their IP offerings for customers.

This theme was reflected at last week’s GlobalFoundries Global Technology Conference when the company’s senior VP of technology and R&D Gregg Bartlett shared details of the foundry’s 28nm high performance plus (HPP) technology, meant to give a performance boost of as much as 10% over the company’s current HP technology. HPP also offers optional ultra-low leakage transistors and SRAMs meant to extend the range of application from high performance down into the low power range.

Navraj Nandra, director of product marketing for mixed-signal IP at Synopsys, confirmed customer demand for IP characterization for packaging because of the speeds that customers are requesting. Logic libraries, CPUs and other IPs are running anywhere between 1 Gbps and 2 Gbps internally, while interfaces are running at 8 Gbps to 10 Gbps.

“That’s great because we can build the IP and we’ve got very smart engineers at Synopsys put that together, but it has to go through a horrible package,” Nandra noted. “I say that because people invest hundreds of billions of dollars on fabs to make transistors go faster but the packaging is still super low-cost. All of this stuff goes into very low cost applications.”

The fast-running protocols are first evident in the data center infrastructure area and then start to transition down into the consumer markets. “When they do that consumers want the performance but they don’t want to pay the price—and that’s where you see a lot of the interesting challenges of getting very, very high-speed signals on-chip and off-chip in very cheap packages where the key careabouts tend to be related to whether you are using flip chip or wire bonds, the type of substrate, length of the bond wire and the distances between the actual bond wires,” he observed.

Added Ken Brock, Synopsys senior staff for product marketing: “We have to start worrying about the I/Os and characterizing the packaging because there is a whole lot of inductance; it’s not just the capacitance that’s a struggle. What it does is set up this funky little resonant frequency that has to be managed. So what is happening at these extreme frequencies, and when you are working with the package, this resonant frequency can come up like the Bay of Fundy with its 53-foot high tides.”

In electrical waves, the results can be disastrous for the chip. “Even just doing a single chip you really have to worry about balancing the capacitance and inductance of the package because these are big chips and are moving very fast,” said Brock, who joined Synopsys from Virage Logic following the acquisition of the company that was completed last Friday.

From a technical perspective, there are a few ways to characterize IP for packaging.
“The first way is really verification in terms of lots of simulations. We talk to package vendors, get a package model, and implement that model in HSPICE. When we are running through the verification of the blocks that we have designed it’s not standalone — we add the package model to the simulation and that gives us a very good understanding of how the package is going to influence the performance, and it does. There’s a loop there where we have to make sure that the package parasitics are not impeding the performance too much,” Nandra said.

For logic libraries it’s usually a simple capacitor and resistor that all the logic cells and memories are characterized to, Brock said.

Synopsys estimates that it spends approximately 10 CPU years simulating a complex piece of IP with all of its resistors, capacitors and inductors. “In terms of hardware characterization, that’s where the fun really starts,” Nandra said, “because there you get the IP packaged in whatever package we were interested at the time and we typically go for something like a BGA—a very low-cost package—typically it’s a bond wire.”

Full characterization is run on that package and the actual IP has been manufactured with split lots so all the process variations have been included in the characterization. Then, a few hundred samples or a few hundred packages will be characterized, meaning that they are automatically put into Synopsys’ test head and go through all the characterization routines at temperature.

For example with USB, he noted, the full suite of electrical tests for USB is performed which could take up to a couple of weeks to finish for one package. However, that provides a pretty good understanding of how the package interacts with the IP under fairly hostile conditions, Nandra concluded.