What’s Your Toggle Rate?

By Luke Lang
Now that power is a key specification, designers are looking into various design techniques to reduce power. One thing that designers realize very quickly is that there is a cost associated with these low-power techniques. Some of these costs are silicon area and design complexity. Very quickly, designers face the tradeoff of cost vs. power saving. In order to analyze this tradeoff, they must first estimate the power dissipation of the design and the power savings of the low-power design techniques. But this is one area where the industry never really had a good answer.

Several years ago, I was talking to an ASIC design manager about power estimation. He was working with a very reputable ASIC foundry, which estimated 32 watts of power dissipation for an ASIC design. The design manager’s company selected the package and designed the system cooling based on this 32 watt estimate. The chip came back and only dissipated 17 watts. The design manager said that this discrepancy cost his company a lot of money on packaging and cooling.

Why did that happen and how can we get better power estimation? As I have mentioned, the industry never really had a good handle on power estimation. We all know that under-estimation of power is death—a huge reliability problem. Since we don’t have a good handle on the issue, it is not surprising that we add lots of margin to the estimated power so that we don’t underestimate. This leads to the overestimation that we often see.

So, why is power estimation so difficult? The library files have well-characterized internal and leakage power tables. Most of them are even characterized for state dependency. It should not be difficult to estimate the internal and leakage power with a good simulation waveform (VCD file). The dynamic power is equally easy to calculate. Just open up any CMOS circuit textbook, and you will see the equation .

At the RTL stage, capacitance (C) loading is certainly difficult to estimate, but it should not be a problem after a trial physical design run. As it turns out, the real problem is determining the toggle rate (F/2). But wait, don’t we get that from the VCD file?

Well, it’s not that simple. If your VCD file is generated from an RTL simulation, then most of the RTL nets do not exist in the netlist. They may be optimized away during synthesis. All you can really count on are I/O and registers being the same between RTL and netlist. You must make sure that your power estimator can propagate the activities from the I/O and registers to the combinational logic gates. Even if your have a VCD file from a gate-level netlist, how do you know if the VCD file represents the worst-case toggle rate?

The problem with most VCD files is that they don’t represent the worst-case toggle rate. If your VCD only has half of the worst-case toggle rate, then you will be severely under-estimating the power. Here are some reasons why most VCD files are not adequate for power estimation. First, most simulation testbenches are written to detect logic errors. They do not represent functional operation of the chip. Second, even if you have a representational functional testbench, you probably cannot run the simulation long enough to be sure that the VCD contains the worst-case toggle rate. Finally, with many designs, you can only run functional test in conjunction with software/firmware. This is just not possible to do with software simulators.

Many designers have turned to hardware emulators to solve the above problems. Hardware emulators run 1,000 to 10,000 times faster than RTL simulators. You can run a lot more cycles to ensure that you have captured the worst-case toggle rate. You can also co-simulate with software/firmware. In fact, I have seen a designer boot up the Linux operating system on a hardware emulator.

Getting a good toggle rate is not only beneficial for power estimation. Many designers do not believe in vector-less IR-drop analysis, which is inherently a guess plus some margin. Many low-power designs are using power (or ground) switches to implement power shut-off. These switches represent resistance in series with that of the power grid. There is just no room for guesswork and margins. Many designers demand the worst-case toggle rate to analyze real IR drop.

Finally, don’t overlook a good set of toggle rate for ATPG patterns, which are notorious for having much higher toggle rates than functional patterns. A large chip can burn up on a tester if power is not well estimated. With excessive toggle rates, a chip of any size can experience significant IR drop and negative impact on yield.

Do you know your toggle rate?

–Luke Lang is a senior product engineering manager at Cadence.