When A Lot May Not Be Enough

For the last couple of months my son has been trying to save for a Nintendo Switch. The emphasis here is on “trying to.” The problem is that whenever he amasses enough money to buy something else, he tends to spend the money on a cheaper toy like a new Lego Dimensions figure. I guess that delayed gratification isn’t really a strength of my son. His assumption is that the best way to collect enough money is to wait for the big events like his birthday and Christmas/New Year rather than carefully putting aside his weekly allowance.

This reminds me a bit of a recent business trip I made to China and Taiwan. Technology companies in both countries have been accelerating their pace of innovation. Consequently, the size of their SoC designs has been growing rapidly as well. While most of these companies have been using FPGA-based prototyping to kick start their software development and complete their hardware/software validation, they have been trying to map their prototypes on a single FPGA.

However, where until recently their designs were small enough to fit on a single FPGA or cut into smaller subsystems for prototyping purposes, they now see a need to prototype bigger (portions of their) designs. Single core became multi-core, multi-core turned into multi cluster, subsystems require more interaction and thus validation of those interactions, the list is growing longer and longer. They can no longer get by with “spending” the FPGA gates whenever they become available. They need to “save up” for bigger, more complex prototypes to match their growing design.

Most of these companies are realizing that the move from single FPGA prototypes to multi-FPGA prototypes is a significant one. Partitioning a design is non-trivial and requires insertion of high-speed TDM (time-division multiplexing) to keep the prototype performance as high as possible. Plus, bring-up of a multi-FPGA prototype requires enough debug observability to more easily find prototype issues.

Multi-FPGA prototyping setup

Because of the more stringent requirements of multi-FPGA requirements, Chinese and Taiwanese technology companies are increasingly adopting integrated prototyping solutions where the FPGA-based prototyping system is designed in harmony with the prototyping software. This offers better performance in context of real world IO, faster time-to-prototype, through better bring-up with automated partitioning and debug capabilities, and scalability from IP prototyping through subsystem and full SoC prototyping.

While current FPGAs offer the equivalent of 10s of millions of ASIC gates, often it is not enough. So time to go big and embrace integrated prototyping to scale your prototyping needs to your growing design.