With Low-Power Comes Great Responsibility

Recent trends in the consumer electronics market show a demand for short, slim, and light-weight but powerful devices (with the only exception being displays, which are getting larger). Therefore area, timing, and power have all become “critical” to design; whereas in the past, one was prioritized over the others depending on design requirements.

However, power is the dominant factor today as consumers want to do everything possible on their handhelds, which have limited battery life but seemingly unlimited applications.

This imposes a huge challenge to the IC designer who is required to churn out low-power chips in ever-shortening time-to-market windows. Traditional design flows do not suffice in such climates. The IC designer needs to make timing, area, and power adjustments upfront, at the RTL, to meet power budgets. For a designer, identifying and exploiting power reduction and power saving opportunities manually is no mean task and can have serious consequences if not done properly. This is where automation becomes essential.

For example, it is not practical for a designer to identify complex enable conditions that can be used for sequential clock gating, as some signals might cross pipeline stages and generate the enable condition. A sequential analysis tool that fully exploits all power saving opportunities in the design through multi-cycle analysis and identification of registers that can be gated is a huge advantage.

Additionally, in order to reduce leakage power, designers need to be able to identify memory gating opportunities and then automate memory gating. In an automated flow, it is extremely important to be able to compute the power versus area and timing trade-offs and generate optimized RTL.

Apart from the automated flow, it is helpful to have a guided optimization flow where the designer is informed about possible power reduction candidates and their cost, in terms of area and timing.

There also may be power saving opportunities in the form of clock gating, memory gating, and data gating. The designer may also like to maintain flexibility and manually patch some part of the RTL in order to conserve timing critical signals, and so forth, before applying any sort of gating.

Designers that use an automated flow combined with a guided optimization flow have reported major power savings in their designs. Power estimation both at the logical level and physical level (after SPEF back-annotation) has yielded extremely promising results. The ultimate power numbers are also close to the estimated power numbers (in the range of 10%).

At a time when the world is full of gizmos and gadgets and consumer electronics companies are under great pressure to deliver quickly and effectively, it becomes necessary to have some kind of automation capability to identify and exploit power reduction opportunities for the chip makers.

Qazi Faheem Ahmed is a Field Applications Engineer with Calypto Design Systems. He can be reached at [email protected]