January 2010


Low-Power And RF Design Heighten Signal-Integrity Concerns


By Ellen Konieczny As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all. For low-power and radio-frequency (RF) designs, which are being prod... » read more

Listening In With Better Audio


By Pallab Chatterjee The high profile discussion on new consumer products has been high definition-video and high-definition TV broadcast. The other end of the experience is starting to catch up with improved audio. Since the shift from LPs and CDs has taken place towards downloadable portable audio data, there have been complaints from the listeners about the quality of the sound. The f... » read more

Should Sign-Off And Implementation Be Separate Tools?


By Ann Steffora Mutschler In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software. Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qua... » read more

Remaking The Design Landscape


By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Apple’s Re-aggregation Anomaly


Apple’s new iPad is an interesting device not so much because of what it offers to consumers—that’s certainly interesting in its own right—but because of how Apple built the device and why. Apple has been scouring the market for seasoned semiconductor engineers of late. The process started two years ago when the company hired a team of former engineers from the late Digital Equipme... » read more

The GSA’s Big Opportunity


By Jack Harding The Global Semiconductor Alliance, the GSA, is at the front lines of a great opportunity. As the semiconductor industry has become a 24-hour-per-day, seven-day-per-week flywheel of activity and innovation, there is only one organization in the world poised to keep pace. It was no stray coincidence that precipitated the renaming of the Fabless Semiconductor Association, the... » read more

Experts At The Table: The Reliability Factor


Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: Is a more complex supply chain cau... » read more

SpyGlass-CDC: Combining Structural And Functional Verification Techniques


Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors--errors that can easily slip past conventional verification tools and make their way into sil... » read more

Carpentry Lessons Applied To ESL


By Jon McDonald Electronic system level design and analysis. How many tools fall under this general description? How many languages are applied in the various stages of system design and analysis? I was recently preparing for a customer presentation in which we were covering most of Mentor’s tools in this area—not all of Mentor’s tools, but a subset of the tools related to the syste... » read more

Value Shift


System Level Design talks with Tom Quan of TSMC, John Koeter of Synopsys, Kalar Rajendiran of eSilicon and Phil Yastrow of Avago about where the value has shifted in the semiconductor design chain and why. [youtube vid=MvSaHSYDqVQ] » read more

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