February 2010 - Page 2 of 2 - Semiconductor Engineering

How Accurate Is Software?

By Ed Sperling - 19 Feb, 2010 - Comments: 0

The number of corner cases is growing. In hardware, that means more verification, more testing and more re-spins. But in software there is no comparable verification method. The Prius braking problem was blamed on a software glitch, but as Synopsys CEO Aart de Geus succinctly noted, none of Toyota’s rivals rushed out to trumpet their own software methodologies. While software adds flexib... » read more

Expert Shootout: Parasitic Extraction

By Ed Sperling - 19 Feb, 2010 - Comments: 0

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: Does parasitic extraction get more complex as we move into multicore chips? And if so, wh... » read more

Smart-Grid Designs Solve Low-Power Riddles

By Various Writers - 11 Feb, 2010 - Comments: 0

By Ellen Konieczny Imagine that you go to your kitchen to get a drink and pass your home’s energy-usage monitor. Due to a recent heat wave, you see that your energy usage is already at what it usually is for the entire month. Yet you’ve still got one week left in your billing cycle. To keep the bill low, you turn your A/C thermostat up a degree and make a mental note to not keep lights o... » read more

Partitioning For Power

By Pallab Chatterjee - 11 Feb, 2010 - Comments: 0

By Pallab Chatterjee Design partitioning for power in an IC is driven by which functions are on simultaneously. The new generation of “smart” power management chips introduces new constraints to the task. Case in point: The new LP8725 from National Semiconductor. These chips have multiple DC-DC converters and both analog and digital low-dropout regulators (LDOs), with a common I2C inter... » read more

The Growing Problem With Parasitic Extraction

By Ed Sperling - 11 Feb, 2010 - Comments: 0

By Ed Sperling Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node. There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. ... » read more

Rethinking Test

By Ann Mutschler - 11 Feb, 2010 - Comments: 0

By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

Expert Shootout: Parasitic Extraction

By Ed Sperling - 11 Feb, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: As we move into 32/28nm, are the parasitics getting worse and is it gett... » read more

Facing Up To Reality

By Ann Mutschler - 10 Feb, 2010 - Comments: 0

Welcome to the world of power awareness. Engineers are well aware that just as timing and area were previously separate considerations in the chip design process, power is also now a top-level consideration. In this blog, we will examine issues related not only to low-power in chip design, but the wide-reaching topic of power-aware design overall. Engineers today must consider the impacts of... » read more

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